公开(公告)号：US12132022B2

公开(公告)日：2024-10-29

申请号：US17430856

申请日：2021-03-08

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Zengyan Fan

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/14 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11019 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14517 ,  H01L2924/35121

摘要： The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device comprises: a semiconductor substrate; a passivation layer, arranged on an upper surface of the semiconductor substrate; a protective layer, arranged on an upper surface of the passivation layer, a dummy opening being formed on the protective layer; and, a dummy bump, partially located in the dummy opening and closely attached to the protective layer.

公开(公告)号：US20240250051A1

公开(公告)日：2024-07-25

申请号：US18627896

申请日：2024-04-05

申请人： ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

发明人： SUMING HU ,  FARSHAD GHAHGHAHI

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/11622 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13541 ,  H01L2224/13552 ,  H01L2224/13582 ,  H01L2224/16227 ,  H01L2224/16238

摘要： In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.

公开(公告)号：US12027487B2

公开(公告)日：2024-07-02

申请号：US18145310

申请日：2022-12-22

申请人： ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

发明人： Cyprian Emeka Uzoh

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13084 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/13684 ,  H01L2224/13686 ,  H01L2224/13805 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16265 ,  H01L2224/16268 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81026 ,  H01L2224/81065 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/83026 ,  H01L2224/83815 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3841

摘要： A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US11984419B2

公开(公告)日：2024-05-14

申请号：US17874021

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hung Chen ,  Yu-Nu Hsu ,  Chun-Chen Liu ,  Heng-Chi Huang ,  Chien-Chen Li ,  Shih-Yen Chen ,  Cheng-Nan Hsieh ,  Kuo-Chio Liu ,  Chen-Shien Chen ,  Chin-Yu Ku ,  Te-Hsun Pang ,  Yuan-Feng Wu ,  Sen-Chi Chiang

IPC分类号： H01L23/00 ,  H01L21/60 ,  H01L23/498

CPC分类号： H01L24/13 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/10145 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/01327 ,  H01L2924/2064 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/13014 ,  H01L2924/00012 ,  H01L2224/13013 ,  H01L2924/00012 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014

摘要： Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

公开(公告)号：US20240128219A1

公开(公告)日：2024-04-18

申请号：US18530286

申请日：2023-12-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hui-Min Huang ,  Wei-Hung Lin ,  Kai Jun Zhan ,  Chang-Jung Hsueh ,  Wan-Yu Chiang ,  Ming-Da Cheng

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02181 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/11622 ,  H01L2224/13018

摘要： A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

公开(公告)号：US20240107780A1

公开(公告)日：2024-03-28

申请号：US18150569

申请日：2023-01-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei WU ,  Ying-Ching SHIH ,  Wen-Chih CHIOU ,  An-Jhih SU ,  Chia-Nan YUAN

IPC分类号： H10B80/00 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48

CPC分类号： H10B80/00 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/08265 ,  H01L2224/119 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193

摘要： A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.

公开(公告)号：US20240088072A1

公开(公告)日：2024-03-14

申请号：US17943580

申请日：2022-09-13

申请人： Micron Technology, Inc.

发明人： Tsung Han Chiang ,  Shin Yueh Yang

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11462 ,  H01L2224/11831 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2924/1436 ,  H01L2924/35121

摘要： Methods, apparatuses, and systems related to embedded metal pads are described. An example semiconductor device includes a dielectric material, a metal pad having side surface, where a lower portion of the side surface is embedded in the dielectric material, a mask material on a portion of a surface of the dielectric material, an upper portion of the side surface of the metal pad, and a portion of a top surface of the metal pad and a contact pillar on a second portion of the top surface of metal pad, the contact pillar comprising a metal pillar and a pillar bump.

公开(公告)号：US11824027B2

公开(公告)日：2023-11-21

申请号：US17092142

申请日：2020-11-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Cheng Chang

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L24/14 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0221 ,  H01L2224/02145 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/06051 ,  H01L2224/11462 ,  H01L2224/11912 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2224/16227 ,  H01L2924/3511

摘要： The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.

公开(公告)号：US20230335531A1

公开(公告)日：2023-10-19

申请号：US18145310

申请日：2022-12-22

申请人： ADEIA SEMICONDUCTOR TECHNOLOGIES LLC

发明人： Cyprian Emeka Uzoh

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/81 ,  H01L24/17 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/11 ,  H01L24/80 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/81026 ,  H01L2224/83026 ,  H01L2224/16501 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2224/16148 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2225/06513 ,  H01L2224/80895 ,  H01L2224/13684 ,  H01L2224/13562 ,  H01L2224/13844 ,  H01L2224/05605 ,  H01L2224/8181 ,  H01L2224/0401 ,  H01L2224/81193 ,  H01L2224/05611 ,  H01L2224/81065 ,  H01L2224/13655 ,  H01L2224/03009 ,  H01L2224/05639 ,  H01L2224/13847 ,  H01L2224/80896 ,  H01L2224/16268 ,  H01L2224/81099 ,  H01L2224/16238 ,  H01L2224/05684 ,  H01L2224/13805 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13686 ,  H01L2224/05572 ,  H01L2224/13019 ,  H01L2224/05616 ,  H01L2224/13084 ,  H01L2224/13809 ,  H01L2224/2919 ,  H01L2224/13564 ,  H01L2224/05644 ,  H01L2224/13855 ,  H01L2224/05609 ,  H01L2224/13811 ,  H01L2224/11009 ,  H01L2224/05571 ,  H01L2224/80357 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/3841 ,  H01L2224/16265

摘要： A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US20230307419A1

公开(公告)日：2023-09-28

申请号：US17821632

申请日：2022-08-23

申请人： Kioxia Corporation

发明人： Soichi HOMMA ,  Chikara MIYAZAKI

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L21/568 ,  H01L24/95 ,  H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2225/06562 ,  H01L2225/06517 ,  H01L2224/11312 ,  H01L2224/11464 ,  H01L2224/11002 ,  H01L2224/11013 ,  H01L2224/95 ,  H01L2224/13018 ,  H01L2224/13147 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8121 ,  H01L2224/81951 ,  H01L2225/06506 ,  H01L2224/48145 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L24/45 ,  H01L2224/48105 ,  H01L24/48 ,  H01L2224/11831

摘要： A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.