公开(公告)号：US20240128211A1

公开(公告)日：2024-04-18

申请号：US18308032

申请日：2023-04-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei WU ,  An-Jhih SU ,  Hua-Wei TSENG ,  Ying-Ching SHIH ,  Wen-Chih CHIOU ,  Chun-Wei CHEN ,  Ming Shih YEH ,  Wei-Cheng WU ,  Der-Chyang YEH

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L24/05 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/08225 ,  H01L2224/16013 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/83097 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/3512 ,  H01L2924/3841

摘要： Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.

公开(公告)号：US20240079381A1

公开(公告)日：2024-03-07

申请号：US18388290

申请日：2023-11-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua YU ,  An-Jhih SU ,  Jing-Cheng LIN ,  Po-Hao TSAI

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/60 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/562 ,  H01L23/60 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/5389 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2924/181

摘要： A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.

公开(公告)号：US20240107780A1

公开(公告)日：2024-03-28

申请号：US18150569

申请日：2023-01-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei WU ,  Ying-Ching SHIH ,  Wen-Chih CHIOU ,  An-Jhih SU ,  Chia-Nan YUAN

IPC分类号： H10B80/00 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48

CPC分类号： H10B80/00 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/08265 ,  H01L2224/119 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193

摘要： A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.

公开(公告)号：US20220181305A1

公开(公告)日：2022-06-09

申请号：US17680789

申请日：2022-02-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua YU ,  An-Jhih SU ,  Jing-Cheng LIN ,  Po-Hao TSAI

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L23/60 ,  H01L25/10 ,  H01L25/00

摘要： A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a curved bottom surface.

公开(公告)号：US20220384213A1

公开(公告)日：2022-12-01

申请号：US17884162

申请日：2022-08-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Yu CHEN ,  An-Jhih SU

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

摘要： A method for forming a chip package structure is provided. The method includes forming a first molding layer surrounding a first chip structure. The method includes disposing a second chip structure over the first chip structure and the first molding layer. The method includes forming a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The method includes forming a third molding layer surrounding the first molding layer and the second molding layer. The method includes disposing a third chip structure over the second chip structure, the second molding layer and the third molding layer. The method includes forming a fourth molding layer surrounding the third chip structure and over the second chip structure, the second molding layer, and the third molding layer.