公开(公告)号：US20240128211A1

公开(公告)日：2024-04-18

申请号：US18308032

申请日：2023-04-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei WU ,  An-Jhih SU ,  Hua-Wei TSENG ,  Ying-Ching SHIH ,  Wen-Chih CHIOU ,  Chun-Wei CHEN ,  Ming Shih YEH ,  Wei-Cheng WU ,  Der-Chyang YEH

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L24/05 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/08225 ,  H01L2224/16013 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/83097 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/3512 ,  H01L2924/3841

摘要： Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.

公开(公告)号：US20240312940A1

公开(公告)日：2024-09-19

申请号：US18123154

申请日：2023-03-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Wei TSAI ,  Chih-Wei WU ,  Ying-Ching SHIH

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L24/16 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16221 ,  H01L2224/17051 ,  H01L2224/81139 ,  H01L2224/81815 ,  H01L2924/182

摘要： A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor module, a reorientation layer, a second semiconductor module and a plurality of jointing materials. The first semiconductor module has at least one first conductive structure and at least one second conductive structure. The reorientation layer covers part of the second conductive structure to form an opening. The second semiconductor module has at least one third conductive structure and at least one fourth conductive structure. The jointing materials are disposed between the first conductive structure and the third conductive structure, and disposed in the opening.

公开(公告)号：US20240107780A1

公开(公告)日：2024-03-28

申请号：US18150569

申请日：2023-01-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei WU ,  Ying-Ching SHIH ,  Wen-Chih CHIOU ,  An-Jhih SU ,  Chia-Nan YUAN

IPC分类号： H10B80/00 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48

CPC分类号： H10B80/00 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/08265 ,  H01L2224/119 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193

摘要： A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.

公开(公告)号：US20230307381A1

公开(公告)日：2023-09-28

申请号：US18319610

申请日：2023-05-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jiun-Ting CHEN ,  Ying-Ching SHIH ,  Szu-Wei LU ,  Chih-Wei WU

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3157 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/73253 ,  H01L2924/3511

摘要： A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar between the first chip structure and the second chip structure. In addition, the chip package structure includes an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate. A topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar.

公开(公告)号：US20210366842A1

公开(公告)日：2021-11-25

申请号：US17392868

申请日：2021-08-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jiun-Ting CHEN ,  Ying-Ching SHIH ,  Szu-Wei LU ,  Chih-Wei WU

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

摘要： A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar over a first portion of the first chip structure and over a second portion of the second chip structure. A width of the anti-warpage bar overlapping the second portion of the second chip structure is greater than a width of the anti-warpage bar overlapping the first portion of the first chip structure.

公开(公告)号：US20150130072A1

公开(公告)日：2015-05-14

申请号：US14079736

申请日：2013-11-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Wei WU ,  Ying-Ching SHIH ,  Szu-Wei LU ,  Jing-Cheng LIN

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

摘要： The embodiments described provide methods and structures for forming support structures between dies and substrate(s) of a three dimensional integrated circuit (3DIC) structures. Each support structure adheres to surfaces of two neighboring dies or die and substrate to relieve stress caused by bowing of the die(s) and/or substrate on the bonding structures formed between the dies or die and substrate. The cost of the support structures is much lower than other processes, such as thermal compression bonding, to reduce the effect of bowing of dies and substrates on 3DIC formation. The support structures improves yield of 3DIC structures.

摘要翻译： 所描述的实施例提供了用于在三维集成电路（3DIC）结构的管芯和衬底之间形成支撑结构的方法和结构。 每个支撑结构粘附在两个相邻的模具或模具和基板的表面上，以减轻由在模具或模具和基板之间形成的结合结构上的模具和/或基板弯曲引起的应力。 支撑结构的成本比其他工艺（例如热压接）要低得多，以减少模具和衬底的弯曲对3DIC形成的影响。 支撑结构提高了3DIC结构的产量。