公开(公告)号：US20240363560A1

公开(公告)日：2024-10-31

申请号：US18766246

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Wei KUO ,  Wen-Shiang LIAO ,  Chewn-Pu JOU ,  Huan-Neng CHEN ,  Lan-Chou CHO ,  William Wu SHEN

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/552 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5225 ,  H01L23/552 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/6622 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1443 ,  H01L2924/146 ,  H01L2924/3025

Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

公开(公告)号：US20240363509A1

公开(公告)日：2024-10-31

申请号：US18645076

申请日：2024-04-24

Applicant: Skyworks Solutions, Inc.

Inventor： Yi Liu ,  Ki Wook Lee ,  Chien Jen Wang ,  Shaul Branchevsky ,  Anthony James LoBianco ,  Reza Kasnavi

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/3121 ,  H01L23/49838

Abstract: A molded package module has a substrate, and multiple interconnect members attached to a bottom side of the substrate. A mold surrounds and extends between the interconnect members. The interconnect members can be electrically and thermally conductive and include a first post portion adjacent the substrate and a second portion adjacent the first post portion so that the first post portion is interposed between the second portion and the substrate. The second portion includes a solderable material. The molded package module can be mounted via a solderable surface at a distal end of the second portion to a motherboard.

公开(公告)号：US20240363508A1

公开(公告)日：2024-10-31

申请号：US18582880

申请日：2024-02-21

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroyuki NOGAWA

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49811 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49838 ,  H01L25/0655

Abstract: A semiconductor module includes: a semiconductor element; a housing for housing the semiconductor element, the housing including a terminal hole; a terminal in the terminal hole and being electrically connected to the semiconductor element; a holding member bonded by an adhesive to the housing; and a potting material in the housing, in which the terminal includes a plate-shaped leg between the holding member and the housing including a recess for accommodating the leg, the recess has a depth greater than a thickness of the leg, in the recess, a portion of the leg in a direction of length of the leg is provided with a passage for the adhesive, the passage being across the leg in a direction of thickness of the leg, and a width of the passage is greater than a difference between the depth of the recess and the thickness of the leg.

公开(公告)号：US12132074B2

公开(公告)日：2024-10-29

申请号：US18306222

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Shiang Liao ,  Chih-Hang Tung

IPC: H01L23/495 ,  H01F27/24 ,  H01F27/28 ,  H01F41/04 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L28/10 ,  H01F27/24 ,  H01F27/2804 ,  H01F41/041 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01F2027/2809 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/95001 ,  H01L2924/1427 ,  H01L2924/19042

Abstract: A package includes a first redistribution structure, a second redistribution structure, an inductor, a permalloy core, and a die. The second redistribution structure is over the first redistribution structure. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure, the third portion is embedded in the second redistribution structure, and the second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor. The die is disposed adjacent to the second portion of the inductor.

公开(公告)号：US12132007B2

公开(公告)日：2024-10-29

申请号：US18103584

申请日：2023-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwan Kim ,  Kyong Hwan Koh ,  Juhyeon Oh ,  Yongkwan Lee

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.

公开(公告)号：US12131971B2

公开(公告)日：2024-10-29

申请号：US17629054

申请日：2019-12-24

Applicant: Sansha Electric Manufacturing Co., Ltd.

Inventor： Shohei Maeda ,  Yoichi Makimoto

IPC: H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H02M7/00

CPC classification number: H01L23/3107 ,  H01L23/13 ,  H01L23/49838 ,  H02M7/003

Abstract: A semiconductor module includes a case accommodating a semiconductor element inside and being entirely molded by a resin, a first terminal placed on a top portion of the case and being a terminal to which a bus bar being a flat and elongated metal conductor is to be attached, a second terminal provided on the top portion of the case and being adjacent to the first terminal, and a rib provided between the first terminal and the second terminal. The rib includes a protrusion protruding toward the bus bar.

公开(公告)号：US20240355724A1

公开(公告)日：2024-10-24

申请号：US18683431

申请日：2021-10-25

Applicant: Mitsubishi Electric Corporation

Inventor： Tatsuya KAWASE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15 ,  H01L23/373 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/15 ,  H01L23/373 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/29 ,  H01L24/30 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/18 ,  H01L2224/29111 ,  H01L2224/3003 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48153 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device includes a first insulating material, a first conductor pattern provided on an upper surface of the first insulating material, a second conductor pattern provided on a lower surface of the first insulating material, a semiconductor element bonded to an upper surface of the first conductor pattern by a first bonding material, and a first base plate bonded to a lower surface of the second conductor pattern by a second bonding material, in which a ratio κ1/D1 satisfies κ1/D1≤35×104W/(m2K) where κ1 represents thermal conductivity of the first insulating material and D1 represents a thickness of the first insulating material, solidus temperature of the first bonding material is equal to or higher than solidus temperature of the second bonding material, and a difference between the solidus temperature of the first bonding material and the solidus temperature of the second bonding material is within 40° C.

公开(公告)号：US12125780B2

公开(公告)日：2024-10-22

申请号：US18527712

申请日：2023-12-04

Applicant: NXP B.V.

Inventor： Mei Yeut Lim

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/49861 ,  H01L21/4839 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48175 ,  H01L2224/4845 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2225/06524

Abstract: A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.

公开(公告)号：US12125778B2

公开(公告)日：2024-10-22

申请号：US18440381

申请日：2024-02-13

Applicant: Liquid Wire Inc.

Inventor： Mark William Ronay ,  Trevor Antonio Rivera ,  Michael Adventure Hopkins ,  Edward Martin Godshalk ,  Charles J. Kinzel

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/4985 ,  H01L23/49861 ,  H01L21/4846

Abstract: A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.

公开(公告)号：US20240347484A1

公开(公告)日：2024-10-17

申请号：US18141202

申请日：2023-04-28

Applicant: SHUNSIN TECHNOLOGY (ZHONG SHAN) LIMITED

Inventor： SHUN-HSING LIAO

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/11334 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81192 ,  H01L2924/182

Abstract: The present disclosure provides a semiconductor package device and a manufacturing method for semiconductor packaging device, the device includes a circuit substrate comprising a first surface and a second surface opposite to the first surface, and a circuit layer disposed between the first surface and the second surface, wherein both the first surface and the second surface are provided with bonding pads; an electronic component disposed on the first surface and electrically connected to the bonding pads of the first surface; a plurality of antenna components spanning the electronic component in a copper bridge manner and electrically connected to the bonding pads on the first surface; and a molding layer formed on the first surface of the circuit substrate, wherein the molding layer surrounds and exposes the plurality of antenna components, and covers the electronic component.