公开(公告)号：US20240363464A1

公开(公告)日：2024-10-31

申请号：US18767895

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

公开(公告)号：US20240363365A1

公开(公告)日：2024-10-31

申请号：US18769434

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hui Cheng ,  Szu-Wei Lu ,  Ping-Yin Hsieh ,  Chih-Hao Chen

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/24175 ,  H01L2224/25171 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

公开(公告)号：US20240355794A1

公开(公告)日：2024-10-24

申请号：US18497039

申请日：2023-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jongkook Kim ,  Chengtar Wu

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3738 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/83 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83862 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/3511

Abstract: A semiconductor package may include: a redistribution layer structure; a semiconductor structure on the redistribution layer structure; a printed circuit board on the redistribution layer structure and extending around a side surface of the semiconductor structure; a molding material extending around the semiconductor structure on the redistribution layer structure; and a silicon interposer on the printed circuit board and the molding material.

公开(公告)号：US12119338B2

公开(公告)日：2024-10-15

申请号：US18447655

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L21/44 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/85399

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US20240332268A1

公开(公告)日：2024-10-03

申请号：US18739690

申请日：2024-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20240321839A1

公开(公告)日：2024-09-26

申请号：US18530542

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Kyounglim Suk ,  Jihwang Kim

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package includes a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern, a first lower semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first lower semiconductor device on the first redistribution structure, a plurality of vertical connection conductors in the molding layer and electrically connected to the first redistribution pattern, a heat dissipation plate disposed on an upper surface of the first lower semiconductor device, and a plurality of upper semiconductor devices disposed on the molding layer and on the first lower semiconductor device, each of the plurality of upper semiconductor devices vertically overlapping a different respective region of the first lower semiconductor device.

公开(公告)号：US20240304606A1

公开(公告)日：2024-09-12

申请号：US18119784

申请日：2023-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wei-Hao CHANG

IPC: H01L25/10 ,  H01L23/552 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/552 ,  H01L25/50 ,  H01L2225/1041 ,  H01L2225/1094

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first circuit layer, a second circuit layer under the first circuit layer, a first electronic component between the first circuit layer and the second circuit layer and connected to the first circuit layer and a sub-package between the first circuit layer and the second circuit layer and connected to the second circuit layer. The sub package comprises a second electronic component under the first electronic component and a conductive structure configured to dissipate heat generated from the first electronic component.

公开(公告)号：US20240304583A1

公开(公告)日：2024-09-12

申请号：US18606973

申请日：2024-03-15

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Jong Sik Paek ,  Doo Hyun Park

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L24/17 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/85 ,  H01L25/105 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2225/1011 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511

Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

公开(公告)号：US12087618B2

公开(公告)日：2024-09-10

申请号：US17231163

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Tang ,  Fu-Chen Chang ,  Cheng-Lin Huang ,  Wen-Ming Chen ,  Chun-Yen Lo ,  Kuo-Chio Liu

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L21/76802 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/67011 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/48 ,  H01L23/481 ,  H01L24/11 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.

公开(公告)号：US12068224B2

公开(公告)日：2024-08-20

申请号：US18080740

申请日：2022-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Szu-Wei Lu

IPC: H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L23/4334 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3675 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/24175 ,  H01L2224/25171 ,  H01L2224/82005 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes a semiconductor die, a thermal conductive through via and a conductive paste. The thermal conductive through via is electrically insulated from the semiconductor die. The conductive paste is disposed over the semiconductor die, wherein the thermal conductive through via is thermally coupled to the semiconductor die through the conductive paste.