公开(公告)号：US12068224B2

公开(公告)日：2024-08-20

申请号：US18080740

申请日：2022-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Szu-Wei Lu

IPC分类号： H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10 ,  H01L25/18

CPC分类号： H01L23/4334 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3675 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/24175 ,  H01L2224/25171 ,  H01L2224/82005 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A semiconductor package includes a semiconductor die, a thermal conductive through via and a conductive paste. The thermal conductive through via is electrically insulated from the semiconductor die. The conductive paste is disposed over the semiconductor die, wherein the thermal conductive through via is thermally coupled to the semiconductor die through the conductive paste.

公开(公告)号：US11854877B2

公开(公告)日：2023-12-26

申请号：US17215493

申请日：2021-03-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Jing-Cheng Lin ,  Ying-Ching Shih ,  Pu Wang ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L21/76877 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48229 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/2919 ,  H01L2924/0655 ,  H01L2924/13091 ,  H01L2924/00

摘要： Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

公开(公告)号：US11562941B2

公开(公告)日：2023-01-24

申请号：US17168186

申请日：2021-02-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Szu-Wei Lu

IPC分类号： H01L23/40 ,  H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/10 ,  H01L25/18 ,  H01L23/31

摘要： A semiconductor package includes a semiconductor die, a first thermal conductive pattern and a second thermal conductive pattern. The semiconductor die is encapsulated by an encapsulant. The first thermal conductive pattern is disposed aside the semiconductor die in the encapsulant. The second thermal conductive pattern is disposed over the semiconductor die, wherein the first thermal conductive pattern is thermally coupled to the semiconductor die through the second thermal conductive pattern and electrically insulated from the semiconductor die.

公开(公告)号：US11257715B2

公开(公告)日：2022-02-22

申请号：US16570046

申请日：2019-09-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00

摘要： A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

公开(公告)号：US11239138B2

公开(公告)日：2022-02-01

申请号：US14318180

申请日：2014-06-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Li-Hui Cheng ,  Po-Hao Tsai ,  Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18 ,  H01L21/48 ,  H01L23/31

摘要： Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.

公开(公告)号：US11205579B2

公开(公告)日：2021-12-21

申请号：US15620590

申请日：2017-06-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu-Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B29C33/12 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

摘要： A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

公开(公告)号：US11081475B2

公开(公告)日：2021-08-03

申请号：US15443827

申请日：2017-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Hsien-Wen Liu ,  Min-Chen Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/525 ,  H01L23/532 ,  H01L23/538 ,  H01L21/56 ,  H01L25/065

摘要： An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

公开(公告)号：US11075168B2

公开(公告)日：2021-07-27

申请号：US16590908

申请日：2019-10-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065

摘要： A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.

公开(公告)号：US20200279836A1

公开(公告)日：2020-09-03

申请号：US16876279

申请日：2020-05-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Jing-Cheng Lin ,  Po-Hao Tsai

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/538 ,  H01L21/48 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

摘要： Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.

公开(公告)号：US20200279750A1

公开(公告)日：2020-09-03

申请号：US16876938

申请日：2020-05-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC分类号： H01L21/321 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/768

摘要： Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.