公开(公告)号：US20240321804A1

公开(公告)日：2024-09-26

申请号：US18489886

申请日：2023-10-19

申请人： Samsung Electronics Co., Ltd.

发明人： Dowan Kim ,  Jieun Woo ,  Unbyoung Kang ,  Seokbong Park

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC分类号： H01L24/20 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2201 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

摘要： A semiconductor package a first package unit comprising a semiconductor chip; and a redistribution structure on the first package unit, wherein the redistribution structure comprises a plurality of wiring lines and a plurality of insulating layers on the plurality of wiring lines, wherein the plurality of wiring lines comprise first subset including a plurality of outermost wiring lines and a second subset, wherein a vertical distance between the plurality of outermost wiring lines and the first package unit is greater than a vertical distance between the second subset of the plurality of wiring lines and the first package unit, a respective surface roughness of each of the plurality of outermost wiring lines is different, and the respective surface roughness of each of the plurality of outermost wiring lines is based on a respective width of each of the plurality of outermost wiring lines in a horizontal direction.

公开(公告)号：US12074127B2

公开(公告)日：2024-08-27

申请号：US18059148

申请日：2022-11-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/482 ,  H01L23/485 ,  H01L23/498 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L24/05 ,  H01L23/48 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/26 ,  H01L24/28 ,  H01L24/29 ,  H01L23/53228 ,  H01L2224/0225 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/19041 ,  H01L2924/35121 ,  H01L2224/13 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2224/05171 ,  H01L2924/01029 ,  H01L2924/013

摘要： A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

公开(公告)号：US20240194621A1

公开(公告)日：2024-06-13

申请号：US18077375

申请日：2022-12-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HSIH-YANG CHIU

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L24/05 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079

摘要： The present application provides a semiconductor structure including a substrate and a conductive member over the substrate. The conductive member includes a seed layer over the substrate, a core disposed over the seed layer, and a protective layer disposed on a top surface of the core and surrounding a sidewall of the core. A method of manufacturing a semiconductor structure is also disclosed.

公开(公告)号：USRE49970E1

公开(公告)日：2024-05-14

申请号：US17213981

申请日：2021-03-26

申请人： IMBERATEK, LLC

发明人： Antti Kivikero ,  Pekka Kostensalo ,  Jaakko Hekki Tapie Moisala

IPC分类号： H05K1/18 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552

CPC分类号： H05K1/18 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/31 ,  H01L24/83 ,  H01L21/4821 ,  H01L23/5386 ,  H01L23/552 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92144 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/0132 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/00

摘要： Disclosed is an electronic module with high routing efficiency and other new possibilities in conductor design. The electronic module comprises a wiring layer (3), a component (1) having a surface with contact terminals (2) and first contact elements (6) that connect at least some of the contact terminals (2) to the wiring layer (3). The electronic module is provided with at least one conducting pattern (4) on the surface of the component (1) but spaced apart from the contact terminals (2). The electronic module further comprises a dielectric (5) and at least one second contact element (7) that connects the conducting pattern (4) to the wiring layer (3) through a portion of said dielectric (5). Methods of manufacturing such modules are also disclosed. An electronic module including a first wiring layer, a dielectric supporting the first wiring layer, wherein the first wiring layer is embedded in the dielectric, a component having a first surface and at least one contact terminal on the first surface, an additional passivation layer on the first surface of the component and in contact with the dielectric, a conducting pattern on the additional passivation layer on the first surface of the component and spaced apart from each of the at least one contact terminal, at least one first contact element extending inside the dielectric for making at least one electrical connection between the first wiring layer and the at least one contact terminal, and at least one second contact element extending inside the dielectric for making at least one electrical connection between the first wiring layer and the conducting pattern.

公开(公告)号：US11935858B2

公开(公告)日：2024-03-19

申请号：US17077646

申请日：2020-10-22

申请人： Samsung Electronics Co., Ltd.

发明人： Seungmin Baek

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0133 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19107 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

摘要： A semiconductor device may include a seed structure on a complex structure. The seed structure may include a first barrier layer, a first seed layer on the first barrier layer, a second barrier layer on the first seed layer, and a second seed layer on the second barrier layer. The second barrier layer may contact a side surface of at least one of the first barrier layer and the first seed layer. An electrode layer may be disposed on the seed structure.

公开(公告)号：US11908816B2

公开(公告)日：2024-02-20

申请号：US17538133

申请日：2021-11-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao Huang

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0239 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05193 ,  H01L2224/13026 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0509 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/05994

摘要： The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.

公开(公告)号：US20240055338A1

公开(公告)日：2024-02-15

申请号：US18218885

申请日：2023-07-06

申请人： Samsung Electronics Co., Ltd.

发明人： Byungho KIM ,  Youngchan KO ,  Gyeongho KIM ,  Yongkoon LEE ,  Myungdo CHO ,  Sangseok HONG

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49822 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L24/32 ,  H01L24/08 ,  H01L2924/15174 ,  H01L2924/13091 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2224/16165 ,  H01L2224/16055 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/32054 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2224/08135

摘要： A fan-out semiconductor package includes a wiring substrate including a first fan-in region, a fan-out region surrounding the first fan-in region, and a second fan-in region, a first fan-in chip structure, a second fan-in chip structure, a first redistribution structure including first redistribution elements disposed on a bottom surface of the wiring substrate, and a second redistribution structure disposed on a top surface of the wiring substrate, and a chip wiring structure formed on a top surface of the second chip, and the second redistribution structure includes a second redistribution layer extending to the first fan-in region and the fan-out region, a plurality of second redistribution vias integrally formed with the second redistribution layer and extending downward, and a seed layer surrounding the second redistribution layer and bottom surfaces of the plurality of second redistribution vias.

公开(公告)号：US20240021548A1

公开(公告)日：2024-01-18

申请号：US17863491

申请日：2022-07-13

申请人： Taiwan Semiconductor Manufacturing Company

发明人： Wei-Chun Liao ,  Guo-Zhou Huang ,  Huan-Kuan Su ,  Yu-Hong Pan ,  Wen Han Hung ,  Ling-Sung Wang

IPC分类号： H01L23/00

CPC分类号： H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/13024 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/05042 ,  H01L2924/0535 ,  H01L2924/07025 ,  H01L2924/35121

摘要： A semiconductor device and method of manufacturing that includes a first etch stop layer and a second etch stop layer to prevent delamination and damage to underlying components. A first passivation layer and a second passivation layer are disposed on a substrate, with a metal pad exposed through the passivation layers and contacting a top metal component of the substrate. The first etch stop layer is then formed on the second passivation layer and the metal pad. A third passivation layer is then formed on the substrate with an opening to the metal pad, which is covered by the first etch stop layer. The second etch stop layer is then formed on the third passivation layer and in the opening on the second etch stop layer. A bottom metal film/conductive component is then formed on the second etch stop layer, photoresist is applied, and wet etching is performed. The metal pad is protected from damage caused by delamination of the second etch stop layer by the first etch stop layer.

公开(公告)号：US11810881B2

公开(公告)日：2023-11-07

申请号：US18073295

申请日：2022-12-01

申请人： ROHM CO., LTD.

发明人： Bungo Tanaka ,  Keiji Wada ,  Satoshi Kageyama

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L23/3107 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05582 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1318 ,  H01L2224/13018 ,  H01L2224/1357 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13647 ,  H01L2224/293 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/181 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/29101 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/293 ,  H01L2924/00014 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/48465 ,  H01L2224/48227 ,  H01L2924/00

摘要： A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

公开(公告)号：US20230343668A1

公开(公告)日：2023-10-26

申请号：US18302627

申请日：2023-04-18

申请人： UTAC Headquarters Pte. Ltd.

发明人： Il Kwon Shim ,  Ronnie M. De Villa ,  Dzafir Bin Mohd Shariff

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/3171 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/20 ,  H01L24/19 ,  H01L23/3185 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2224/02381 ,  H01L2224/05083 ,  H01L2224/05111 ,  H01L2224/05008 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05571 ,  H01L2224/0401 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/245 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24011 ,  H01L2224/05082 ,  H01L2224/05027 ,  H01L2224/05024 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/13124 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13116 ,  H01L2224/13113 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L23/49866 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2224/2101

摘要： A semiconductor device has a substrate and a first insulating layer formed over a first major surface of the substrate. A first redistribution layer is formed over the first insulating layer. A second insulating layer is formed over the first redistribution layer. A second redistribution layer can be formed over the second insulating layer, and a third insulating layer can be formed over the second redistribution layer. A protection layer is formed over a second major surface of the substrate for warpage control. A conductive layer is formed over the first redistribution layer, and a bump is formed over the conductive layer. An under bump metallization can be formed under the bump. The protection layer extends over a side surface of the substrate between the first major surface and second major surface. The protection layer further extends over a side surface of the first insulating layer.