公开(公告)号：US20240363570A1

公开(公告)日：2024-10-31

申请号：US18141456

申请日：2023-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jose Daniel Carlos Torres ,  Katleen Fajardo Timbol

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L23/31 ,  H01L23/4951 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05672 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11831 ,  H01L2224/13018 ,  H01L2224/13147 ,  H01L2224/16245

Abstract: A semiconductor package comprises an integrated circuit having a contact and a conductive bump directly attached to the contact. The conductive bump has a sidewall with a roughened surface. A leadframe is electrically coupled to the conductive bump. An integrated circuit package mold covers portions of the conductive bump and the lead frame, the roughened surface of the conductive bump is configured to interlock with the integrated circuit package mold. An electrically conductive adhesive couples the conductive bump to the lead frame. The conductive bump comprises copper in one arrangement. The roughened surface of the conductive bump includes grooves along grain boundaries that separate copper grains. The roughened surface of the conductive bump is formed by etching with a diluted sulfuric peroxide solution.

公开(公告)号：US20240363549A1

公开(公告)日：2024-10-31

申请号：US18613040

申请日：2024-03-21

Applicant: Innolux Corporation

Inventor： Wei-Yuan Cheng ,  Ju-Li Wang

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/367 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L23/562 ,  H01L21/4846 ,  H01L23/367 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/33 ,  H01L25/16 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/13105 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204

Abstract: An electronic device includes a substrate, a circuit layer, at least one electronic unit, a stress adjustment layer, and a buffer layer. The substrate has a first surface and a second surface opposite to each other and at least one side connected to the first surface and the second surface. The circuit layer is disposed on the first surface of the substrate. The at least one electronic unit is electronically connected to the circuit layer. The stress adjustment layer is disposed on the second surface of the substrate. The buffer layer surrounds the substrate, wherein the stress adjustment layer is located between the substrate and the buffer layer, and the buffer layer is in contact with the at least one side of the substrate.

公开(公告)号：US12132024B2

公开(公告)日：2024-10-29

申请号：US17460301

申请日：2021-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai ,  Tzuan-Horng Liu ,  Cheng-Chieh Hsieh ,  Tsung-Yuan Yu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/96 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16238 ,  H01L2224/2205 ,  H01L2224/73265 ,  H01L2924/1815

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.

公开(公告)号：US12132019B2

公开(公告)日：2024-10-29

申请号：US18151622

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/06182 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/08225 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2224/83099 ,  H01L2224/8389 ,  H01L2224/92142 ,  H01L2225/06541 ,  H01L2225/06548

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US20240355783A1

公开(公告)日：2024-10-24

申请号：US18757428

申请日：2024-06-27

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

公开(公告)号：US20240355763A1

公开(公告)日：2024-10-24

申请号：US18761075

申请日：2024-07-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： En Hao HSU ,  Kuo Hwa TZENG ,  Chia-Pin CHEN ,  Chi Long TSAI

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/022 ,  H01L2224/02377 ,  H01L2224/13018

Abstract: An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.

公开(公告)号：US20240355745A1

公开(公告)日：2024-10-24

申请号：US18759008

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/075 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0753 ,  H01L25/167 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US12125828B2

公开(公告)日：2024-10-22

申请号：US18464855

申请日：2023-09-11

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Ching Ho ,  Bo-Hao Ma ,  Yu-Ting Xue ,  Ching-Hung Tseng ,  Guan-Hua Lu ,  Hong-Da Chang

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5226 ,  H01L24/13 ,  H01L2225/06541

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

公开(公告)号：US20240347495A1

公开(公告)日：2024-10-17

申请号：US18752274

申请日：2024-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio FONTANA

IPC: H01L23/00 ,  G01N21/956 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/19 ,  G01N21/95684 ,  H01L21/565 ,  H01L23/3185 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L25/0652

Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.

公开(公告)号：US12119321B2

公开(公告)日：2024-10-15

申请号：US17947536

申请日：2022-09-19

Applicant: EPISTAR CORPORATION

Inventor： Shih-An Liao ,  Shau-Yi Chen ,  Ming-Chi Hsu ,  Chun-Hung Liu ,  Min-Hsun Hsieh

IPC: H01L23/48 ,  H01L23/00 ,  H01L33/62 ,  H01L33/30 ,  H01L33/64

CPC classification number: H01L24/16 ,  H01L24/06 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L33/62 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L33/30 ,  H01L33/647 ,  H01L2224/04105 ,  H01L2224/0612 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13499 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16227 ,  H01L2224/165 ,  H01L2224/2929 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/83886 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/12041 ,  H01L2924/15156 ,  H01L2224/29344 ,  H01L2924/00014 ,  H01L2224/29347 ,  H01L2924/00014 ,  H01L2224/29324 ,  H01L2924/00014 ,  H01L2224/29355 ,  H01L2924/00014 ,  H01L2224/29339 ,  H01L2924/00014 ,  H01L2224/29313 ,  H01L2924/00014 ,  H01L2224/29309 ,  H01L2924/00014 ,  H01L2224/29311 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2224/29311 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/2939 ,  H01L2924/00014 ,  H01L2224/294 ,  H01L2924/00014 ,  H01L2224/83203 ,  H01L2924/00012

Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stack structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface of the carrier; and a conductive connecting layer comprising a first conductive part, comprising a first outer contour, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conductive part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conductive part to form a covering area, wherein the first bonding surface comprises a first position which is the closest to the carrier within the covering area and a second position which is the farthest from the carrier within the covering area in a cross section view, and a distance from the first position to the first out contour is greater than that from the second position to the first outer contour.