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公开(公告)号：US12176282B2
公开(公告)日：2024-12-24
申请号：US18190935
申请日：2023-03-27
Inventor： Chung-Ming Weng , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Cheng-Chieh Hsieh , Hung-Yi Kuo , Tsung-Yuan Yu , Hua-Kuei Lin , Hsiu-Jen Lin , Ming-Che Ho , Yu-Hsiang Hu , Chewn-Pu Jou , Cheng-Tse Tang
IPC: H01L23/498 , G02B6/42 , H01L21/768 , H01L23/00
Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.
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公开(公告)号：US20240069277A1
公开(公告)日：2024-02-29
申请号：US17898427
申请日：2022-08-29
Inventor： Hung-Yi Kuo , Chen-Hua Yu , Cheng-Chieh Hsieh , Che-Hsiang Hsu , Chung-Ming Weng , Tsung-Yuan Yu
IPC: G02B6/12 , G02B6/34 , G02B6/42 , H01L21/56 , H01L25/065
CPC classification number: G02B6/12004 , G02B6/34 , G02B6/4201 , H01L21/56 , H01L25/0652 , G02B2006/12104 , G02B2006/12114
Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die. The at least one reflector is disposed on the at least one prism structure.
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公开(公告)号：US20230378140A1
公开(公告)日：2023-11-23
申请号：US18363731
申请日：2023-08-01
Inventor： Hao-Yi Tsai , Cheng-Chieh Hsieh , Tsung-Hsien Chiang , Hui-Chun Chiang , Tzu-Sung Huang , Ming-Hung Tseng , Kris Lipu Chuang , Chung-Ming Weng , Tsung-Yuan Yu , Tzuan-Horng Liu
IPC: H01L25/065 , H01L23/00 , H01L25/00 , H01L25/10
CPC classification number: H01L25/0657 , H01L24/03 , H01L24/05 , H01L25/50 , H01L25/105 , H01L24/08 , H01L24/02 , H01L2224/73204 , H01L2225/06586 , H01L2225/06513 , H01L2225/06544 , H01L2225/06548 , H01L2224/0557 , H01L2224/05559 , H01L2224/05573 , H01L2224/05647 , H01L24/06 , H01L2224/06135 , H01L2224/0311 , H01L2224/0312 , H01L2224/02141 , H01L2224/08225 , H01L2225/1035 , H01L2225/1058 , H01L24/73
Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.
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公开(公告)号：US11768338B2
公开(公告)日：2023-09-26
申请号：US17332988
申请日：2021-05-27
Inventor： Chung-Ming Weng , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Cheng-Chieh Hsieh , Hung-Yi Kuo , Tsung-Yuan Yu , Hua-Kuei Lin , Yu-Hsiang Hu , Chewn-Pu Jou , Feng-Wei Kuo
CPC classification number: G02B6/4214 , G02B6/12002 , G02B6/12004 , G02B6/136 , G02B6/4203 , G02B6/4204 , G02B6/43 , G02B6/428 , G02B2006/12102 , G02B2006/12104
Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.
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公开(公告)号：US20220299719A1
公开(公告)日：2022-09-22
申请号：US17206130
申请日：2021-03-19
Inventor： Tsung-Yuan Yu , Hung-Yi Kuo , Cheng-Chieh Hsieh , Hao-Yi Tsai , Chung-Ming Weng , Hua-Kuei Lin , Che-Hsiang Hsu
Abstract: A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.
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公开(公告)号：US11043463B2
公开(公告)日：2021-06-22
申请号：US16923739
申请日：2020-07-08
Inventor： Wen-Hsiung Lu , Hsuan-Ting Kuo , Tsung-Yuan Yu , Hsien-Wei Chen , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/00 , H01L21/768 , H01L23/525 , H01L23/532 , H01L23/29 , H01L23/31 , H01L21/56
Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
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公开(公告)号：US10262964B2
公开(公告)日：2019-04-16
申请号：US15942692
申请日：2018-04-02
Inventor： Wen-Hsiung Lu , Hsuan-Ting Kuo , Tsung-Yuan Yu , Hsien-Wei Chen , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/00 , H01L23/29 , H01L21/56 , H01L23/31 , H01L23/532 , H01L23/525 , H01L21/768
Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
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公开(公告)号：US10079213B2
公开(公告)日：2018-09-18
申请号：US15169177
申请日：2016-05-31
Inventor： Hsien-Wei Chen , Tsung-Yuan Yu , Ming-Da Cheng , Wen-Hsiung Lu
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00 , H01L21/78 , H01L21/56 , H01L23/58 , H01L23/544 , H01L23/31
CPC classification number: H01L23/562 , H01L21/56 , H01L21/78 , H01L23/3114 , H01L23/544 , H01L23/585 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/96 , H01L2223/5446 , H01L2224/02331 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05548 , H01L2224/13 , H01L2224/13022 , H01L2224/13024 , H01L2224/94 , H01L2924/3512 , H01L2924/35121 , H01L2924/3656 , H01L2224/11
Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.
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公开(公告)号：US09935070B2
公开(公告)日：2018-04-03
申请号：US14991426
申请日：2016-01-08
Inventor： Wen-Hsiung Lu , Hsuan-Ting Kuo , Tsung-Yuan Yu , Hsien-Wei Chen , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L21/00 , H01L23/00 , H01L21/768 , H01L23/525 , H01L23/532 , H01L23/29 , H01L23/31 , H01L21/56
CPC classification number: H01L24/11 , H01L21/566 , H01L21/76885 , H01L23/293 , H01L23/3192 , H01L23/525 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/02331 , H01L2224/0345 , H01L2224/0347 , H01L2224/036 , H01L2224/0362 , H01L2224/03828 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05186 , H01L2224/05548 , H01L2224/05569 , H01L2224/05582 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/10126 , H01L2224/1112 , H01L2224/11334 , H01L2224/1134 , H01L2224/11462 , H01L2224/1148 , H01L2224/1181 , H01L2224/11849 , H01L2224/1191 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16238 , H01L2224/81191 , H01L2224/814 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2924/04953 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/00
Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
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公开(公告)号：US20180076135A1
公开(公告)日：2018-03-15
申请号：US15804407
申请日：2017-11-06
Inventor： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Tsung-Yuan Yu
IPC: H01L23/522 , H01L29/06 , H01L27/06 , H01L27/08 , H01L49/02 , H01L23/58 , H01L21/768 , H01L21/311
CPC classification number: H01L23/5227 , H01L21/31144 , H01L21/76802 , H01L21/76877 , H01L23/585 , H01L27/0688 , H01L27/08 , H01L28/10 , H01L29/0619 , H01L2924/0002 , H01L2924/00
Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.
