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1.发明授权公开(公告)号：US12132155B2
公开(公告)日：2024-10-29
申请号：US17145752
申请日：2021-01-11
Applicant: Micron Technology, Inc.
Inventor： Vladimir Odnoblyudov , Scott D. Schellhammer , Jeremy S. Frei
IPC: H01L33/52 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/00 , H01L23/31 , H01L33/00 , H01L33/20 , H01L33/44 , H01L33/62 , H01S5/02 , H10K50/84 , H10K50/844 , H10K71/00
CPC classification number: H01L33/52 , H01L21/561 , H01L21/78 , H01L23/3185 , H01L33/0095 , H01L33/20 , H01L33/44 , H01L33/62 , H01S5/0201 , H01L21/6836 , H01L24/11 , H01L24/13 , H01L24/97 , H01L2221/68327 , H01L2221/68377 , H01L2224/1146 , H01L2224/13022 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/97 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2933/005 , H01L2933/0066 , H10K50/84 , H10K50/844 , H10K71/00 , H10K71/851 , Y02P80/30 , H01L2224/97 , H01L2224/11 , H01L2224/1146 , H01L2924/00014 , H01L2224/13124 , H01L2924/00014 , H01L2224/13147 , H01L2924/00014 , H01L2224/13144 , H01L2924/00014 , H01L2224/13139 , H01L2924/00014 , H01L2924/12041 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2924/12044 , H01L2924/00
Abstract: Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially encapsulated in a dielectric material.
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公开(公告)号：US12107064B2
公开(公告)日：2024-10-01
申请号：US17719390
申请日：2022-04-13
Inventor： Jen-Jui Yu , Chih-Chiang Tsao , Hsuan-Ting Kuo , Mao-Yen Chang , Hsiu-Jen Lin , Ching-Hua Hsieh , Hao-Jan Pei
IPC: H01L23/00 , H01L23/367 , H01L23/498 , H01L25/18
CPC classification number: H01L24/16 , H01L23/367 , H01L23/49822 , H01L24/13 , H01L24/29 , H01L24/73 , H01L24/81 , H01L25/18 , H01L2224/13109 , H01L2224/13113 , H01L2224/13139 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/92125
Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).
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公开(公告)号：US20240321823A1
公开(公告)日：2024-09-26
申请号：US18531883
申请日：2023-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donguk Kwon , Gongmyeong Kim , Sunchul Kim , Chaein Moon , Hyeonrae Cho
CPC classification number: H01L24/83 , H01L21/481 , H01L23/3128 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/18 , H10B80/00 , H01L24/48 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/16227 , H01L2224/32237 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/81193 , H01L2224/83102 , H01L2224/83385 , H01L2224/92125 , H01L2924/014 , H01L2924/1431 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1441 , H01L2924/1443
Abstract: Provided is a semiconductor package with enhanced reliability and a method of manufacturing the same. The semiconductor package includes a package substrate including a body layer having a central area and a peripheral area, a first protective layer on a top surface of the body layer, and a second protective layer on the first protective layer in the peripheral area, a semiconductor chip mounted on the first protective layer in the central area in a flip-chip structure, an underfill in a gap between the first protective layer and the semiconductor chip and in a gap between the connection terminals, an interposer on the semiconductor chip, and inter-substrate connection terminals on the peripheral area of the package substrate and electrically connecting the package substrate to the interposer, where the underfill has an anchor structure extending into the first protective layer.
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公开(公告)号：US20240312787A1
公开(公告)日：2024-09-19
申请号：US18590491
申请日：2024-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jose Franco A. Alicante , Roderick S. Balares , Christopher Abenes , Jeniffer Otero Aspuria
IPC: H01L21/304 , H01L21/56 , H01L21/683 , H01L23/00
CPC classification number: H01L21/304 , H01L21/561 , H01L21/6836 , H01L24/81 , H01L24/13 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/81
Abstract: Backgrinding a semiconductor wafer includes planarizing backgrind tape without requiring cutting the tape. A semiconductor substrate is provided with an active top surface and a back surface. The active top surface includes a plurality of bumps that connect to devices formed in or on the substrate. A backgrind tape is applied over the top surface of the substrate. The backgrind tape covers the bumps and extends to a periphery of the top surface. The top surface of the substrate is placed so that the backgrind tape is positioned on a chuck table of a backgrind apparatus. Pressure is applied to the back surface of the substrate forcing the backgrind tape against the chuck table. The pressure is removed after a predetermined interval. Backgrinding is performed on the back surface of the substrate to reach a target substrate thickness.
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公开(公告)号：US20240290737A1
公开(公告)日：2024-08-29
申请号：US18418320
申请日：2024-01-21
Applicant: MEDIATEK INC.
Inventor： Hung-Pin Tsai , Pei-Haw Tsao , Nai-Wei Liu , Wen-Sung Hsu
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02381 , H01L2224/0239 , H01L2224/03 , H01L2224/0401 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05184 , H01L2224/05557 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/11 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155
Abstract: A bump structure includes a conductive pad on a semiconductor die; a passivation layer covering a perimeter of the conductive pad; and a first polymer layer on the passivation layer. The first polymer layer includes a via opening partially exposing the central portion of the conductive pad. A RDL is disposed on the first polymer layer and patterned into a bump pad situated directly above the conductive pad. The via opening is completely filled with the RDL and a RDL via is integrally formed with the bump pad. A second polymer layer is disposed on the first polymer layer. An island of the second polymer layer is disposed at a central portion of the bump pad. UBM layer is disposed on the bump pad. The UBM layer covers the island and forms a bulge thereon. A bump is disposed on the UBM layer.
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公开(公告)号：US20240266340A1
公开(公告)日：2024-08-08
申请号：US18163416
申请日：2023-02-02
Inventor： Chih-Chao CHOU , Yi-Hsun CHIU , Shang-Wen CHANG , Ching-Wei TSAI , Chih-Hao WANG
IPC: H01L25/00 , H01L23/00 , H01L23/522 , H01L23/528 , H01L25/065
CPC classification number: H01L25/50 , H01L23/5226 , H01L23/5286 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/80 , H01L25/0652 , H01L25/0657 , H01L21/6835 , H01L25/18 , H01L2221/68327 , H01L2221/68359 , H01L2221/68381 , H01L2224/05571 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05669 , H01L2224/05684 , H01L2224/08145 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/80006 , H01L2224/80357 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2924/014 , H01L2924/0544 , H01L2924/059
Abstract: A package structure and a formation method are provided. The method includes disposing a first chip structure over a carrier substrate. The first chip structure has a front-side interconnection structure facing the carrier substrate. The method also includes forming a back-side interconnection structure over the first chip structure. The first chip structure has a device portion between the back-side interconnection structure and the front-side interconnection structure. The back-side interconnection structure has stacked conductive vias. The method further includes bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding.
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公开(公告)号：US20240266334A1
公开(公告)日：2024-08-08
申请号：US18165772
申请日：2023-02-07
Inventor： Ke-Gang Wen , Liang-Wei Wang , Dian-Hau Chen , Tsung-Chieh Hsiao
CPC classification number: H01L25/105 , H01L24/13 , H01L24/16 , H01L24/24 , H01L25/50 , H10B80/00 , H01L24/32 , H01L24/73 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/24227 , H01L2224/32221 , H01L2224/73253 , H01L2225/1035 , H01L2225/1094
Abstract: An integrated semiconductor device is provided. The integrated semiconductor device includes a first semiconductor structure having a first IC, and a second semiconductor structure stacked above the first semiconductor structure and having a second IC. The second semiconductor structure has a first surface facing the first semiconductor structure and a second surface facing away from the first semiconductor structure. The integrated semiconductor device also includes a thermal dissipation structure having a first portion partially through the first IC and a second portion fully through the second semiconductor structure and exposed at the second surface of the second semiconductor structure. The second portion may be outside of the second IC.
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公开(公告)号：US20240266267A1
公开(公告)日：2024-08-08
申请号：US18637737
申请日：2024-04-17
Applicant: NANYA TECHNOLOGY CORPORATION
Inventor： PEI CHENG FAN
IPC: H01L23/498 , H01L21/48 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H01L23/49816 , H01L21/4853 , H01L21/486 , H01L23/49833 , H01L23/49838 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L24/04 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/73 , H01L2224/0401 , H01L2224/05551 , H01L2224/05555 , H01L2224/05563 , H01L2224/13111 , H01L2224/13139 , H01L2224/16055 , H01L2224/16057 , H01L2224/16227 , H01L2224/73204
Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.
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公开(公告)号：US20240258252A1
公开(公告)日：2024-08-01
申请号：US18430074
申请日：2024-02-01
Inventor： Ching-Yu CHANG , Ming-Da CHENG , Ming-Hui WENG
CPC classification number: H01L24/05 , C08G73/1078 , C08G73/1085 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02251 , H01L2224/0226 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03616 , H01L2224/0401 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05176 , H01L2224/05181 , H01L2224/05184 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11849 , H01L2224/13026 , H01L2224/13082 , H01L2224/13111 , H01L2224/13116 , H01L2224/13118 , H01L2224/1312 , H01L2224/13123 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13149 , H01L2224/13155 , H01L2224/1316 , H01L2224/13166 , H01L2224/13171 , H01L2224/13179 , H01L2224/1318 , H01L2224/13181 , H01L2224/13184 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/07025
Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.
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公开(公告)号：US12040294B2
公开(公告)日：2024-07-16
申请号：US18313560
申请日：2023-05-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ju-Il Choi , Un-Byoung Kang , Jin Ho An , Jongho Lee , Jeonggi Jin , Atsushi Fujisaki
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0346 , H01L2224/03614 , H01L2224/0401 , H01L2224/05016 , H01L2224/0508 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/11849 , H01L2224/13026 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155
Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.
