公开(公告)号：US11876064B2

公开(公告)日：2024-01-16

申请号：US17429305

申请日：2020-06-15

申请人： ChangXin Memory Technologies, Inc.

发明人： Ling-Yi Chuang

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/13005 ,  H01L2224/2745 ,  H01L2224/2902

摘要： A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.

公开(公告)号：US20180197738A1

公开(公告)日：2018-07-12

申请号：US15786090

申请日：2017-10-17

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L45/00 ,  H01L21/027 ,  H01L21/31 ,  H01L21/28 ,  H01L51/00

CPC分类号： H01L21/0337 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L45/1675 ,  H01L51/0018 ,  H01L2224/0362 ,  H01L2224/11622

摘要： A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US09773724B2

公开(公告)日：2017-09-26

申请号：US13753312

申请日：2013-01-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Ting Chen ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/488 ,  H01L23/544 ,  H01L21/768 ,  H01L25/00

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0348 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/06102 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1161 ,  H01L2224/11618 ,  H01L2224/11622 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13187 ,  H01L2224/1319 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/00012 ,  H01L2924/00

摘要： Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.

公开(公告)号：US09768134B2

公开(公告)日：2017-09-19

申请号：US14608466

申请日：2015-01-29

申请人： Micron Technology, Inc.

发明人： Anilkumar Chandolu ,  Kenneth N. Hagen

IPC分类号： H01L21/4763 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

CPC分类号： H01L24/13 ,  H01L22/14 ,  H01L22/20 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02215 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03914 ,  H01L2224/03916 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05565 ,  H01L2224/0557 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/05688 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/11632 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0474 ,  H01L2924/0503 ,  H01L2924/05994 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/05432

摘要： A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

公开(公告)号：US09704826B2

公开(公告)日：2017-07-11

申请号：US15186624

申请日：2016-06-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh ,  Kuo-Chung Yee ,  Jui-Pin Hung

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/027 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L21/66

CPC分类号： H01L25/0652 ,  H01L21/0273 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11616 ,  H01L2224/11622 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2924/00012

摘要： A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

公开(公告)号：US20170053883A1

公开(公告)日：2017-02-23

申请号：US15254948

申请日：2016-09-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： You Chye How ,  Huay Yann Tay

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49589 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02205 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11618 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13078 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13616 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/92225 ,  H01L2924/01327 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces.

摘要翻译： 一种集成电路（“IC”）封装，包括至少一个IC裸片，其具有第一侧和至少两个相邻的凸块焊盘和与第一侧相对的第二侧; 第一基板，其上具有多个电接触表面的第一侧; 以及多个铜柱，每个铜柱具有附接到相邻凸块之一的第一端和连接到电接触表面之一的第二端。

公开(公告)号：US20160276300A1

公开(公告)日：2016-09-22

申请号：US15054413

申请日：2016-02-26

申请人： SEIKO EPSON CORPORATION

发明人： Yoshihide MATSUO ,  Masashi YOSHIIKE

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2002/14241 ,  B41J2002/14491 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05655 ,  H01L2224/1161 ,  H01L2224/11618 ,  H01L2224/11622 ,  H01L2224/13008 ,  H01L2224/1319 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16227 ,  H01L2224/27618 ,  H01L2224/27622 ,  H01L2224/27901 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/29024 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/301 ,  H01L2224/30145 ,  H01L2224/32237 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81444 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83455 ,  H01L2224/83466 ,  H01L2224/83471 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/0635 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/0615 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2224/27848 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83

摘要： An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

摘要翻译： 电子装置包括：压电元件的驱动基板（压力室基板和振动板），与形成在其上的压电元件的驱动有关的电极布线;以及密封板，电极布线由布线金属 金（Au）通过作为基底层的粘合层在驱动基板上，并且具有去除部分，其中在包含粘合到接合树脂的部分的区域中的布线金属的一部分被去除并且粘附层暴露 。

公开(公告)号：US20150262949A1

公开(公告)日：2015-09-17

申请号：US14259432

申请日：2014-04-23

申请人： LSI Corporation

发明人： John W. Osenbach ,  Steven D. Cate

IPC分类号： H01L23/00

CPC分类号： H01L21/00 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/118 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81447 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/37 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/206 ,  H01L2224/03

摘要： A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow pillars are formed by electroplating metal into the second openings for a second time period during which the metal is also added to the metal layers in the first openings to form wide pillars having substantially the same height as the narrow pillars. The photoresist is then removed along with conductive layers on the device used as part of the plating process.

摘要翻译： 一种在倒装芯片上形成金属柱的工艺。 支柱以及一层焊料将用于将器件上的管芯焊盘与衬底上相应的衬底焊盘接合。 光致抗蚀剂沉积在器件上，并形成光致抗蚀剂中的第一个开口。 金属层通过将金属电镀第一次开始形成。 然后将光致抗蚀剂图案化以形成具有比第一开口小的直径的第二开口。 通过将金属电镀到第二开口中第二时间段来形成窄柱，在此期间金属也被添加到第一开口中的金属层，以形成具有与窄柱基本相同的高度的宽支柱。 然后将光致抗蚀剂与用作电镀工艺的一部分的器件上的导电层一起除去。

公开(公告)号：US09029257B2

公开(公告)日：2015-05-12

申请号：US13952481

申请日：2013-07-26

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi

IPC分类号： H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

摘要翻译： 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。

公开(公告)号：US20140367837A1

公开(公告)日：2014-12-18

申请号：US14303371

申请日：2014-06-12

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chun-Che LEE ,  Yuan-Chang SU ,  Wen-Chi CHENG ,  Guo-Cheng LIAO ,  Yi-Chuan DING

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

摘要： The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

摘要翻译： 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。