专利检索 cpc:"H01L2224/11903" 第 1 页

1.

再颁专利
Multiple plated via arrays of different wire heights on a same substrate 有权

公开(公告)号：USRE49987E1

公开(公告)日：2024-05-28

申请号：US17725442

申请日：2022-04-20

申请人： Invensas LLC

发明人： Cyprian Emeka Uzoh , Rajesh Katkar

IPC分类号： H01L25/065 , B81B7/00 , B81C1/00 , H01L21/48 , H01L23/00 , H01L23/367 , H01L23/42 , H01L23/48 , H01L23/498 , H01L23/522 , H01L23/538 , H01L25/00 , H01L25/16 , H01L49/02

CPC分类号： H01L25/0657 , B81B7/0074 , B81C1/0023 , H01L21/4853 , H01L23/3675 , H01L23/42 , H01L23/481 , H01L23/49811 , H01L23/522 , H01L23/5383 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/24 , H01L24/49 , H01L24/73 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/16 , H01L25/50 , H01L28/10 , H01L28/20 , H01L28/40 , H01L24/02 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/81 , H01L2224/0239 , H01L2224/0332 , H01L2224/0333 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03614 , H01L2224/0391 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/04042 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05184 , H01L2224/05547 , H01L2224/05565 , H01L2224/05568 , H01L2224/05569 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/05684 , H01L2224/1134 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11903 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/13565 , H01L2224/13616 , H01L2224/1403 , H01L2224/14131 , H01L2224/14132 , H01L2224/14134 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2224/17181 , H01L2224/24147 , H01L2224/24227 , H01L2224/244 , H01L2224/32145 , H01L2224/3303 , H01L2224/33181 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48149 , H01L2224/4903 , H01L2224/73201 , H01L2224/73253 , H01L2224/73265 , H01L2224/81192 , H01L2224/81193 , H01L2224/81825 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/12042 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/16251 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/3841 , H01L2924/01322 , H01L2924/00 , H01L2924/15787 , H01L2924/00 , H01L2924/15788 , H01L2924/00 , H01L2924/181 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2224/0239 , H01L2924/01029 , H01L2224/131 , H01L2924/014 , H01L2224/05568 , H01L2924/00014 , H01L2224/13147 , H01L2924/00014 , H01L2224/81825 , H01L2924/00014 , H01L2224/1147 , H01L2924/00014 , H01L2224/0347 , H01L2924/00014 , H01L2224/05147 , H01L2924/00014 , H01L2224/05647 , H01L2924/00014 , H01L2224/05124 , H01L2924/00014 , H01L2224/05624 , H01L2924/00014 , H01L2224/05111 , H01L2924/00014 , H01L2224/05611 , H01L2924/00014 , H01L2224/05169 , H01L2924/00014 , H01L2224/05669 , H01L2924/00014 , H01L2224/05155 , H01L2924/00014 , H01L2224/05655 , H01L2924/00014 , H01L2224/05144 , H01L2924/00014 , H01L2224/05644 , H01L2924/00014 , H01L2224/05184 , H01L2924/00014 , H01L2224/05684 , H01L2924/00014 , H01L2224/05139 , H01L2924/00014 , H01L2224/05639 , H01L2924/00014 , H01L2224/0345 , H01L2924/00014 , H01L2224/03452 , H01L2924/00014 , H01L2224/0332 , H01L2924/00014 , H01L2224/03462 , H01L2924/00014 , H01L2224/03464 , H01L2924/00014 , H01L2224/11462 , H01L2924/00014 , H01L2224/11464 , H01L2924/00014 , H01L2224/0333 , H01L2924/00012 , H01L2224/13616 , H01L2924/00014 , H01L2224/05616 , H01L2924/00014 , H01L2224/13155 , H01L2924/01074 , H01L2224/13184 , H01L2924/01028 , H01L2224/13124 , H01L2924/00014 , H01L2224/13111 , H01L2924/01082 , H01L2224/13155 , H01L2924/00014 , H01L2224/13144 , H01L2924/00014 , H01L2224/13139 , H01L2924/00014 , H01L2224/13116 , H01L2924/00014 , H01L2224/13113 , H01L2924/00014 , H01L2224/13169 , H01L2924/00014 , H01L2224/73201 , H01L2224/05 , H01L2224/13 , H01L2224/94 , H01L2224/81 , H01L2224/48091 , H01L2924/00014 , H01L2224/45147 , H01L2924/00 , H01L2224/97 , H01L2224/81 , H01L2224/45147 , H01L2924/00014 , H01L2224/45015 , H01L2924/20751 , H01L2224/45015 , H01L2924/20752 , H01L2224/45015 , H01L2924/20753 , H01L2224/45015 , H01L2924/20754 , H01L2224/45015 , H01L2924/20755 , H01L2224/45015 , H01L2924/20756 , H01L2224/45015 , H01L2924/20757 , H01L2224/45015 , H01L2924/20758 , H01L2224/45015 , H01L2924/20759 , H01L2224/45015 , H01L2924/2076 , H01L2924/00014 , H01L2224/45015 , H01L2924/20751 , H01L2924/00014 , H01L2224/45015 , H01L2924/20752 , H01L2924/00014 , H01L2224/45015 , H01L2924/20753 , H01L2924/00014 , H01L2224/45015 , H01L2924/20754 , H01L2924/00014 , H01L2224/45015 , H01L2924/20755 , H01L2924/00014 , H01L2224/45015 , H01L2924/20756 , H01L2924/00014 , H01L2224/45015 , H01L2924/20757 , H01L2924/00014 , H01L2224/45015 , H01L2924/20758 , H01L2924/00014 , H01L2224/45015 , H01L2924/20759 , H01L2924/00014 , H01L2224/45015 , H01L2924/2076 , H01L2924/00014 , H01L2224/45099

摘要： Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.

2.

发明授权
Copper pillar sidewall protection 有权

公开(公告)号：US09875980B2

公开(公告)日：2018-01-23

申请号：US14286263

申请日：2014-05-23

申请人： Amkor Technology, Inc.

发明人： Glenn Rinne , Dean Zehnder , Christopher J. Berry , Robert Lanzone , Ludovico Bancod

IPC分类号： H01L23/00 , H01L23/498 , H01L21/48

CPC分类号： H01L24/13 , H01L21/4846 , H01L23/49811 , H01L23/49894 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/05567 , H01L2224/10145 , H01L2224/10175 , H01L2224/1146 , H01L2224/1147 , H01L2224/11474 , H01L2224/1182 , H01L2224/11831 , H01L2224/11849 , H01L2224/119 , H01L2224/11903 , H01L2224/13017 , H01L2224/13021 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13565 , H01L2224/1357 , H01L2224/1369 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/32238 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/83192 , H01L2924/15311 , H01L2924/3651 , H01L2224/32225 , H01L2924/00 , H01L2924/00014 , H01L2924/014

摘要： Methods for copper pillar protection may include forming a metal post over a contact on a semiconductor die, where the metal post comprises a sidewall. A metal cap may be formed on the metal post and may be wider than the width of the metal post. A solder bump may be formed on the metal cap, and a conformal passivation layer may be formed on at least the sidewall of the metal post. The metal cap may be rounded shaped or rectangular shaped in cross-section. The metal post and the metal cap may comprise copper. The metal cap may comprise a copper layer and a nickel layer. The seed metal layer may comprise one or more of titanium, tungsten, and copper. The conformal passivation layer may comprise a nonwettable polymer. Horizontal portions of the conformal passivation layer may be removed utilizing an anisotropic etch such as a plasma etch.

3.

发明授权
Semiconductor device and manufacturing method thereof 有权

公开(公告)号：US09818709B2

公开(公告)日：2017-11-14

申请号：US15098138

申请日：2016-04-13

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Hiroyuki Utsunomiya

IPC分类号： H01L23/48 , H01L23/52 , H01L21/44 , H01L21/4763 , H01L23/00

CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0345 , H01L2224/03462 , H01L2224/03831 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/10145 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13005 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/16237 , H01L2224/81191 , H01L2224/81193 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81469 , H01L2224/81815 , H01L2924/206 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012 , H01L2924/014

摘要： A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.

4.

发明授权
Substrate interconnections having different sizes 有权

公开(公告)号：US09773755B2

公开(公告)日：2017-09-26

申请号：US14860362

申请日：2015-09-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Wei Shen , Ying-Ching Shih , Chen-Shien Chen , Ming-Fa Chen

IPC分类号： H01L25/00 , H01L25/065 , H01L23/00 , H01L23/498 , H01L21/48 , H01L23/538 , H01L23/31

CPC分类号： H01L25/0657 , H01L21/486 , H01L23/3114 , H01L23/3192 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/81 , H01L25/0655 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/0381 , H01L2224/03831 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/1162 , H01L2224/11622 , H01L2224/1181 , H01L2224/11849 , H01L2224/11903 , H01L2224/13016 , H01L2224/13025 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13169 , H01L2224/1354 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81193 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06568 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2224/05552 , H01L2924/00

摘要： A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

5.

发明授权
Self aligned bump passivation 有权
标题翻译：自对准凸块钝化

公开(公告)号：US09543262B1

公开(公告)日：2017-01-10

申请号：US13892585

申请日：2013-05-13

申请人： Cypress Semiconductor Corporation

发明人： William W. C. Koutney, Jr.

IPC分类号： H01L23/00

CPC分类号： H01L24/11 , H01L24/02 , H01L24/05 , H01L24/13 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0239 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/03831 , H01L2224/03914 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05548 , H01L2224/05624 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/119 , H01L2224/11903 , H01L2224/1191 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13147 , H01L2224/16227 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01013 , H01L2924/013 , H01L2924/00012 , H01L2924/01028 , H01L2924/01022 , H01L2924/01024 , H01L2224/0231

摘要： A method of fabricating multiple conductor layers utilizing the same seed layer is described. In an embodiment a stud bump structure is described in which the seed layer is encapsulated by the passivation layer. By forming the stud bump prior to the passivation layer, the height of the stud bump extending from the top surface of the passivation layer can be controlled.

摘要翻译： 描述了利用相同种子层制造多个导体层的方法。在一个实施例中，描述了柱形凸起结构，其中种子层被钝化层封装。通过在钝化层之前形成柱形凸块，可以控制从钝化层的顶表面延伸的柱形凸块的高度。

6.

发明申请
Reliable Device Assembly 有权
标题翻译：可靠的装置装配

公开(公告)号：US20160329290A1

公开(公告)日：2016-11-10

申请号：US15212603

申请日：2016-07-18

申请人： Invensas Corporation

发明人： Belgacem Haba , Charles G. Woychik , Cyprian Emeka Uzoh , Michael Newman , Terrence Caskey

IPC分类号： H01L23/00

CPC分类号： H01L24/13 , H01L21/563 , H01L23/564 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/02372 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05147 , H01L2224/05155 , H01L2224/05557 , H01L2224/05568 , H01L2224/05571 , H01L2224/05609 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/10145 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11903 , H01L2224/13024 , H01L2224/13025 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/1319 , H01L2224/14517 , H01L2224/1601 , H01L2224/16057 , H01L2224/16058 , H01L2224/16104 , H01L2224/16105 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16503 , H01L2224/17505 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81001 , H01L2224/81007 , H01L2224/811 , H01L2224/81139 , H01L2224/8192 , H01L2224/83104 , H01L2224/9201 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H05K1/181 , H05K3/30 , Y10T29/4913 , H01L2924/00012 , H01L2924/01015 , H01L2924/01074 , H01L2224/05552

摘要： Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

摘要翻译： 本文公开了微电子组件及其制造方法。在一个实施例中，形成微电子组件的方法包括组装第一和第二部件以使第一和第二部件的第一主表面彼此面对并且彼此隔开预定间隔，第一部件具有第一和第二相对主表面，在第一和第二主表面之间沿第一方向延伸的第一厚度和在第一主表面处的多个第一金属连接元件，第二部件在第一主要部分具有多个第二金属连接元件第二部件的表面; 以及电镀多个金属连接器区域，每个金属连接器区域在第一方向上在相应的第一连接元件和与相应的第一连接元件相对的相应的第二连接元件之间连续延伸。

7.

发明申请
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法

公开(公告)号：US20160322322A1

公开(公告)日：2016-11-03

申请号：US15098138

申请日：2016-04-13

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Hiroyuki UTSUNOMIYA

IPC分类号： H01L23/00

CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0345 , H01L2224/03462 , H01L2224/03831 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/10145 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13005 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/16237 , H01L2224/81191 , H01L2224/81193 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81469 , H01L2224/81815 , H01L2924/206 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012 , H01L2924/014

摘要： A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.

摘要翻译： 在使用Cu柱的倒装芯片安装中提供了具有高可靠性的倒装芯片安装技术。在通过Cu柱与安装板耦合的半导体装置中，使Cu柱从下方依次具有包括柱层，阻挡层和凸块的层叠结构，并且将凸块形成为小于阻挡层。

8.

发明授权
Semiconductor packaging structure and method 有权
标题翻译：半导体封装结构及方法

公开(公告)号：US09293338B2

公开(公告)日：2016-03-22

申请号：US14074687

申请日：2013-11-07

申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

发明人： Chang-Ming Lin , Yu-Juan Tao

IPC分类号： H01L21/285 , H01L23/00 , H01L21/28 , H01L23/36 , H01L23/367 , H01L23/498 , H01L23/31

CPC分类号： H01L23/485 , H01L21/28 , H01L21/28587 , H01L23/3121 , H01L23/3142 , H01L23/3192 , H01L23/36 , H01L23/3675 , H01L23/3677 , H01L23/48 , H01L23/482 , H01L23/49838 , H01L23/49861 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/83 , H01L24/94 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0239 , H01L2224/0345 , H01L2224/0361 , H01L2224/03612 , H01L2224/03614 , H01L2224/03912 , H01L2224/0401 , H01L2224/05025 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/06102 , H01L2224/1132 , H01L2224/11462 , H01L2224/1147 , H01L2224/1182 , H01L2224/11825 , H01L2224/11849 , H01L2224/119 , H01L2224/11903 , H01L2224/1191 , H01L2224/13024 , H01L2224/13076 , H01L2224/13082 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13541 , H01L2224/13562 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13609 , H01L2224/13611 , H01L2224/13639 , H01L2224/13644 , H01L2224/13655 , H01L2224/14051 , H01L2224/16055 , H01L2224/16058 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/17106 , H01L2224/17519 , H01L2224/73204 , H01L2224/81191 , H01L2224/81424 , H01L2224/81447 , H01L2224/831 , H01L2224/92 , H01L2224/92125 , H01L2224/94 , H01L2924/12042 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/2064 , H01L2924/20641 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/0231 , H01L21/304 , H01L21/78 , H01L2224/81 , H01L2924/00

摘要： A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals.

摘要翻译： 提供半导体封装方法。该方法包括提供半导体衬底。半导体衬底具有第一表面和第二表面，以及在半导体衬底的第一表面上的电镀籽晶层。该方法还包括在电镀种子层上形成多个柱状电极，其中柱状电极包括第一柱状电极和第二柱状电极。此外，该方法包括在第一柱状电极和第二柱状电极上形成扩散阻挡层，在第一柱状电极上的扩散阻挡层上形成多个第一焊球。该方法还包括提供具有对应于第一焊球的焊接端子的封装基板，并将半导体基板安装在翻转位置的封装基板上，使得第一焊球与焊接端子连接。

9.

发明授权
Mixed-sized pillars that are probeable and routable 有权
标题翻译：混合尺寸的支柱，可探测和可路由

公开(公告)号：US09263409B2

公开(公告)日：2016-02-16

申请号：US14283108

申请日：2014-05-20

申请人： eSilicon Corporation

发明人： Javier DeLaCruz

IPC分类号： H01L23/48 , H01L23/00 , G01R31/28

CPC分类号： H01L24/14 , G01R31/2884 , H01L24/13 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/1415 , H01L2224/1416 , H01L2224/16227 , H01L2224/1703 , H01L2924/01029 , H01L2924/1461 , H01L2924/00 , H01L2924/00014 , H01L2924/014

摘要： An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and multiple macro-pillars also attached to the surface of the integrated circuit. The micro-pillars provide an electrical interface to the integrated circuit during regular operation. The macro-pillars provide an electrical interface to the integrated circuit both during regular operation and during testing of the integrated circuit.

摘要翻译： 公开了一种具有可探测和可路由接口的集成电路。集成电路包括附接到集成电路的表面的多个微柱，以及也附接到集成电路的表面的多个宏支柱。微柱在正常操作期间为集成电路提供电接口。在常规操作期间和在集成电路测试期间，宏观支柱为集成电路提供电接口。