公开(公告)号：US12057435B2

公开(公告)日：2024-08-06

申请号：US17723981

申请日：2022-04-19

申请人： Samsung Electronics Co., Ltd.

发明人： Hyeonseok Lee ,  Jongyoun Kim ,  Seokhyun Lee

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

CPC分类号： H01L25/0655 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16014 ,  H01L2224/16055 ,  H01L2224/16058 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2924/182

摘要： A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

公开(公告)号：US20240250007A1

公开(公告)日：2024-07-25

申请号：US18358644

申请日：2023-07-25

申请人： SanDisk Technologies LLC

发明人： Hiroki Yabe

IPC分类号： H01L23/498 ,  G11C7/18 ,  G11C16/28 ,  H01L23/00 ,  H01L25/065 ,  H10B43/35

CPC分类号： H01L23/49822 ,  G11C7/18 ,  G11C16/28 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H10B43/35 ,  H01L2224/08055 ,  H01L2224/08145 ,  H01L2224/16055 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1438 ,  H01L2924/1815

摘要： Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

公开(公告)号：US12035472B2

公开(公告)日：2024-07-09

申请号：US18220026

申请日：2023-07-10

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Akito Yoshida ,  Mahmoud Dreiza ,  Curtis Michael Zwenger

IPC分类号： H05K1/11 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40

CPC分类号： H05K1/14 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/10 ,  H01L24/16 ,  H01L24/81 ,  H05K1/11 ,  H05K1/181 ,  H05K1/184 ,  H05K1/185 ,  H05K3/303 ,  H05K3/34 ,  H05K3/363 ,  H05K3/4007 ,  H01L23/3171 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01079 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10977 ,  H05K2203/043 ,  Y10T29/49165 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A

公开(公告)号：US09837369B2

公开(公告)日：2017-12-05

申请号：US15023716

申请日：2013-09-27

申请人： Renesas Electronics Corporation

发明人： Yoshikazu Shimote ,  Shinji Baba ,  Toshihiro Iwasaki ,  Kazuyuki Nakagawa

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L21/78 ,  H05K3/28 ,  H05K3/34 ,  H01L21/683

CPC分类号： H01L24/17 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L23/564 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16055 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1713 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/2064 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/09427 ,  H05K2201/10704 ,  H05K2201/10977 ,  H05K2203/0465 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/45099 ,  H01L2924/207

摘要： In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

公开(公告)号：US09741675B2

公开(公告)日：2017-08-22

申请号：US14599366

申请日：2015-01-16

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Dao-Long Chen ,  Ping-Feng Yang ,  Chang-Chi Lee ,  Chien-Fan Chen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0614 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1414 ,  H01L2224/16055 ,  H01L2224/16056 ,  H01L2224/81191 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

公开(公告)号：US20170194274A1

公开(公告)日：2017-07-06

申请号：US15387016

申请日：2016-12-21

申请人： Amkor Technology, Inc.

发明人： Bora Baloglu ,  Curtis Zwenger ,  Ron Huemoeller

IPC分类号： H01L23/00 ,  H01L25/10

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/0558 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1147 ,  H01L2224/13018 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1405 ,  H01L2224/16055 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/80203 ,  H01L2224/81005 ,  H01L2224/81141 ,  H01L2224/81203 ,  H01L2224/8134 ,  H01L2224/81385 ,  H01L2224/81898 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/01028 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01074

摘要： A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

公开(公告)号：US09691694B2

公开(公告)日：2017-06-27

申请号：US14703290

申请日：2015-05-04

申请人： QUALCOMM Incorporated

发明人： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang ,  Mario Francisco Velez

IPC分类号： H01L23/48 ,  H01L21/336 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/50

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

摘要： An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

公开(公告)号：US09581638B2

公开(公告)日：2017-02-28

申请号：US13905958

申请日：2013-05-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Cheng Wu ,  Li-Han Hsu ,  Sao-Ling Chiu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Lin

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： H01L22/14 ,  G01R1/07314 ,  G01R31/265 ,  G01R31/2884 ,  H01L22/12 ,  H01L22/32 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1713 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596

摘要： An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.

摘要翻译： 一种实施方式包括提供晶片芯片（CoW）结构的标准化测试结构设计，其中标准化测试结构设计包括将测试结构放置在CoW结构中的顶部模具的预选区域内，并且电测试 通过在测试结构上应用通用测试探针卡，在CoW结构中的多个微胶片。

公开(公告)号：US20170047304A1

公开(公告)日：2017-02-16

申请号：US14823021

申请日：2015-08-11

申请人： LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.

发明人： JOSEPH KUCZYNSKI ,  MELISSA K. MILLER ,  HEIDI D. WILLIAMS ,  JING ZHANG

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  B23K1/00 ,  H05K3/34

CPC分类号： H01L24/17 ,  B23K1/0016 ,  B23K3/0623 ,  H01L23/3142 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/11011 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/81007 ,  H01L2224/81815 ,  H01L2924/06 ,  H01L2924/14 ,  H01L2924/1531 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/613

摘要： Example methods, apparatus, and products for creating an environmentally protective coating for integrated circuit assemblies are described herein. A preform plastic sheet is places over components of an integrated circuit such that during a reflow process, the preform plastic sheet melts to form a conformal coating over components of the integrated circuit assembly.

摘要翻译： 本文描述了用于为集成电路组件创建环境保护涂层的示例性方法，设备和产品。 预成型塑料片位于集成电路的部件之上，使得在回流工艺期间，预制塑料片熔化以在集成电路组件的部件上形成共形涂层。

公开(公告)号：US09508686B2

公开(公告)日：2016-11-29

申请号：US14563982

申请日：2014-12-08

申请人： Micron Technology, Inc.

发明人： Chan Yoo ,  Todd O. Bolken

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L21/82 ,  H01L23/495

CPC分类号： H01L25/105 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/495 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06177 ,  H01L2224/1012 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/12105 ,  H01L2224/1301 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/83

摘要： Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

摘要翻译： 本文公开了制造半导体器件的方法。 根据特定实施例配置的方法包括在密封剂上形成间隔物材料，使得密封剂将间隔物材料与半导体器件的有源表面和远离有源表面突出的至少一个互连件分开。 该方法还包括模制密封剂，使得互连件的至少一部分延伸穿过密封剂并进入隔离材料。 互连可以包括与半导体器件的有源表面基本共面的接触表面，用于提供与半导体器件的电连接。