公开(公告)号：US20250072095A1

公开(公告)日：2025-02-27

申请号：US18762561

申请日：2024-07-02

Applicant: Huahong ZealCore Electronics Technology Co.,Ltd

Inventor： Yimin WAN ,  Xiaojun WANG ,  Qinghai MA ,  Xiuzhong WANG ,  Rong CHEN ,  Haiming BAO

IPC: H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/417

Abstract: A terminal structure with optimized reliability for a power semiconductor device, a preparation method therefor, application thereof, a power device and a preparation method therefor are provided. The terminal structure includes a phosphorus-doped silicon oxide layer, a silicon nitride layer, a silicon-rich silicon nitride semi-insulating layer, an undoped silicon dioxide layer, and an organic medium layer. The silicon-rich silicon nitride semi-insulating layer is of an alternating superposition structure of a silicon-rich silicon nitride layer and an ultra-thin silicon nitride barrier layer. The terminal structure effectively prevents external moisture from invading the power device, which improves the robustness of the power device under a moisture condition. The multi-layer silicon-rich silicon nitride is used as a semi-insulating layer, which makes an electric field on a surface of the power device evenly distributed in gradient, prevents the electric field from being gathered at a device terminal.

公开(公告)号：US12237413B2

公开(公告)日：2025-02-25

申请号：US18447783

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

Inventor： Lianjie Li ,  Feng Han ,  Jian-Hua Lu ,  Yanbin Lu ,  Shui Liang Chen

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

Abstract: An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

公开(公告)号：US12237402B2

公开(公告)日：2025-02-25

申请号：US17994780

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Wei Hsu ,  Yu-Jen Shen ,  Hao-Yun Cheng ,  Chih-Wei Wu ,  Ying-Tsung Chen ,  Ying-Ho Chen

IPC: H01L21/3105 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

公开(公告)号：US12237394B2

公开(公告)日：2025-02-25

申请号：US18226262

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US12237213B2

公开(公告)日：2025-02-25

申请号：US17631932

申请日：2021-11-12

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Libin Zhang ,  Yayi Wei ,  Zhen Song

IPC: H01L21/768 ,  H01L29/40 ,  G03F7/09

Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1. The photolithographic coating is exposed to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film. The photolithographic coating is exposed to a light having a second wavelength through a mask, to image the mask to a second region of the photolithographic film. A region in which the first region and the second region overlap serves as a connection region corresponding to the to-be-connected structure, and thereby self-alignment between a layer of the to-be-connected structure and a layer where a contact hole is arranged is implemented.

公开(公告)号：US20250063774A1

公开(公告)日：2025-02-20

申请号：US18234083

申请日：2023-08-15

Applicant: Nami MOS CO., LTD.

Inventor： FU-YUAN HSIEH ,  LIN XU

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/40 ,  H01L29/78

Abstract: An improved SiC trench MOSFET having N-type and P-type shield zones for gate oxide electric-field reduction is disclosed. The N-type shield zones are formed below a gate electrode and the P-type shield zones adjoin lower surfaces of the body regions. The device further comprises a current spreading region surrounding at least sidewalls of the gate trenches for on-resistance reduction.

公开(公告)号：US20250063747A1

公开(公告)日：2025-02-20

申请号：US18719223

申请日：2022-11-24

Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

Inventor： Masaki HASHIMOTO ,  Ryuji SUEMOTO ,  Satoru SENDA

IPC: H01L29/872 ,  H01L29/40

Abstract: [Problem] To provide a semiconductor device capable of suppressing a channel current without increasing manufacturing processes, and capable of accurately forming a channel current suppression structure. [Solution] A semiconductor device 1 according to the present invention includes: a substrate 10; an epitaxial layer 20 formed on the substrate 10; and an insulating film 35 provided on one surface 20a side of the epitaxial layer 20. An active portion 40 provided with a predetermined element and a channel current suppression portion 50 being at a termination portion 70 side and provided outside the active portion 40 are provided on the one surface 20a side of the epitaxial layer 20 via the insulating layer 35. The channel current suppression portion 50 is provided with a trench 51 for suppressing the channel current flowing from the active portion 40 to the termination portion 70.

公开(公告)号：US12230709B2

公开(公告)日：2025-02-18

申请号：US17815233

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tung-Yang Lin ,  Hsueh-Liang Chou

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

Abstract: Present disclosure provides a transistor structure, including a substrate, a first gate extending along a longitudinal direction over the substrate, the first gate including a gate electrode, a second gate over the substrate and apart from the first gate, a source region of a first conductivity type in the substrate, aligning to an edge in proximity to a side of the first gate, a P-type well surrounding the source region, a drain region of the first conductivity type in the substrate, an N-type well surrounding the drain region, the second gate is entirely within a vertical projection area of the N-type well and a bottom surface of the P-type well and a bottom surface of the N-type well are substantially at a same depth from the first gate.

公开(公告)号：US12230705B2

公开(公告)日：2025-02-18

申请号：US17729460

申请日：2022-04-26

Applicant: Nami MOS CO., LTD.

Inventor： Fu-Yuan Hsieh

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein the termination trenches surrounds outer periphery of gate trenches and do not surround said gate metal pad area; Inner edges of a first termination trench of the termination trenches adjacent to trench ends of the gate trenches have a plurality of wave shape portions in regions between two adjacent trench ends of the gate trenches while outer edges have a straight shape to reduce drain-source leakage current. Each of gate trenches on which has at least one shielded gate trench contact connected to a shielded gate electrode, and the shielded gate trench contact is spaced apart from any of multiple gate metal runners with a distance larger than 100 um.

公开(公告)号：US12230509B2

公开(公告)日：2025-02-18

申请号：US17029021

申请日：2020-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming Thai Chai ,  Meng Xie ,  Wenbo Ding

IPC: H01L21/324 ,  H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to the gate structure; performing a first cleaning process; performing a first rapid thermal anneal (RTA) process to remove oxygen cluster in the substrate; forming a metal layer on the source/drain region; and performing a second RTA process to transform the metal layer into a silicide layer.