-
1.发明公开公开(公告)号：US20240355921A1
公开(公告)日：2024-10-24
申请号：US18238947
申请日：2023-08-28
发明人： Sen HUANG , Qimeng JIANG , Xinyue DAI , Xinhua WANG , Xinyu LIU
IPC分类号： H01L29/778 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7789 , H01L29/08 , H01L29/41725 , H01L29/4236 , H01L29/66462 , H01L29/7783
摘要： The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.
-
公开(公告)号：US12124945B2
公开(公告)日：2024-10-22
申请号：US17310203
申请日：2019-01-28
发明人： Hangbing Lv , Xiaoxin Xu , Qing Luo , Ming Liu
CPC分类号： G06N3/065 , G11C11/223 , G11C11/2273 , G11C11/54 , H01L29/516 , H01L29/78391
摘要： Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.
-
3.发明授权公开(公告)号：US12107046B2
公开(公告)日：2024-10-01
申请号：US17597907
申请日：2019-07-31
发明人： Gang Zhang , Zongliang Huo
IPC分类号： H01L23/528 , H01L21/768 , H01L23/535
CPC分类号： H01L23/5283 , H01L21/76805 , H01L21/76816 , H01L21/76895 , H01L23/535
摘要： Provided is an L-shaped stepped word line structure including: L-shaped word line units, each including a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction. A word line terminal included in the short side is formed in a stepped stacked layer structure including stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region including a short side region surface/internal metal layer respectively located on a surface/in an interior. In a first direction, a length of the short side region surface metal layer is greater than that of the short side region internal metal layer, and the word line terminal corresponds to the short side region surface metal layer.
-
公开(公告)号：US12088323B2
公开(公告)日：2024-09-10
申请号：US18254377
申请日：2020-11-25
发明人： Qi Wang , Yiyang Jiang , Qianhui Li , Zongliang Huo , Tianchun Ye
CPC分类号： H03M13/3905 , G11C29/1201 , G11C29/42 , G11C29/46
摘要： A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.
-
公开(公告)号：US12068757B2
公开(公告)日：2024-08-20
申请号：US17907048
申请日：2020-03-23
发明人： Qi Wang , Yiyang Jiang , Qianhui Li , Zongliang Huo
IPC分类号： H03M13/11 , H03M13/15 , H03M13/39 , G06F11/00 , G11C29/52 , H03M13/25 , H03M13/29 , H03M13/37 , H03M13/45
CPC分类号： H03M13/1111 , H03M13/154 , H03M13/3927 , G06F11/00 , G11C29/52 , H03M13/1108 , H03M13/255 , H03M13/2948 , H03M13/3746 , H03M13/45
摘要： The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.
-
公开(公告)号：US20240220355A1
公开(公告)日：2024-07-04
申请号：US18553929
申请日：2021-04-08
发明人： Qianhui LI , Qi WANG , Liu YANG , Yiyang JIANG , Xiaolei YU , Jing HE , Zongliang HUO , Tianchun YE
IPC分类号： G06F11/10
CPC分类号： G06F11/1008
摘要： A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.
-
公开(公告)号：US20240176228A1
公开(公告)日：2024-05-30
申请号：US17773668
申请日：2021-11-08
发明人： Jianfang HE , Yayi WEI , Yajuan SU , Lisong DONG , Libin ZHANG , Rui CHEN , Le MA
摘要： The present disclosure provides a method for optimizing mask parameters, and the method includes: acquiring a test pattern, light source parameters, and initial mask parameters, the initial mask parameters including a mask thickness and an initial mask sidewall angle; generating multiple sets of candidate mask parameters according to the initial mask sidewall angle in the initial mask parameters; the multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness; obtaining an imaging contrast of each set of candidate mask parameters based on the test pattern and the light source parameters; and selecting an optimal mask sidewall angle from the multiple sets of candidate mask parameters according to the imaging contrasts. By generating multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness, and simulating these sets of candidate mask parameters respectively, the imaging contrast of each set of candidate mask parameters is obtained, so that the optimal mask sidewall angle is found according to the imaging contrasts. Therefore, by optimizing the mask parameters of the multi-layer film lens structure, the imaging contrast can also be significantly improved, and the imaging resolution can be improved.
-
8.发明授权公开(公告)号：US11942474B2
公开(公告)日：2024-03-26
申请号：US18172802
申请日：2023-02-22
发明人： Huilong Zhu
IPC分类号： H01L29/66 , H01L21/77 , H01L25/065 , H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L21/77 , H01L25/0657 , H01L29/66712 , H01L29/7802
摘要： A method of manufacturing a parallel structure of semiconductor devices includes: disposing a semiconductor stack, which includes source/drain layers disposed vertically in sequence and channel layers therebetween, on a substrate; patterning the semiconductor stack into a predetermined shape to define an active region; forming gate stacks around at least part of peripheries of the channel layers; forming an isolation layer on peripheries of the active region and the gate stack; forming first to third conductive channels on a sidewall of the isolation layer; determining the pre-determined shape and a shape of the gate stacks, such that one of the source/drain layers on two sides of the channel layer passes through the isolation layer to contact the first conductive channel, while the other one passes through the isolation layer to contact the second conductive channel, and the gate stack passes through the isolation layer to contact the third conductive channel.
-
公开(公告)号：US11930720B2
公开(公告)日：2024-03-12
申请号：US17495390
申请日：2021-10-06
发明人： Meiyin Yang , Jun Luo , Yan Cui , Jing Xu
CPC分类号： H10N52/80 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , G11C11/22 , H10B61/00 , H10N52/00 , G11C11/1659
摘要： The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode. The second metal interconnection portion is connected to the ferroelectric thin film layer, and the fourth metal interconnection portion is connected to the tunnel junction. As compared with the prior art, the present disclosure can control a directional flipping of the magnetic moment in the tunnel junction based on the ferroelectric thin film layer provided. Based on the structural design of the storage unit, the present disclosure does not require an external magnetic field, and fully meets the requirement of high integration of the device.
-
公开(公告)号：US11929304B2
公开(公告)日：2024-03-12
申请号：US17666790
申请日：2022-02-08
发明人： Huilong Zhu , Tianchun Ye
CPC分类号： H01L23/46 , H01L21/4871
摘要： A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.
-
-
-
-
-
-
-
-
-
搜索结果
584 条记录 (耗时 0.033 秒)
