公开(公告)号：US20240362110A1

公开(公告)日：2024-10-31

申请号：US18771080

申请日：2024-07-12

申请人： InterDigital Technology Corporation

发明人： Kyle Jung-Lin Pan

IPC分类号： G06F11/10 ,  H03M13/29 ,  H04B7/0413 ,  H04B7/0456 ,  H04B7/06 ,  H04L1/00 ,  H04L1/1607 ,  H04L1/1812 ,  H04L1/1829 ,  H04L5/00 ,  H04L25/03 ,  H04W72/21

CPC分类号： G06F11/1004 ,  H03M13/2957 ,  H04B7/0413 ,  H04B7/0456 ,  H04B7/0632 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/0073 ,  H04L1/0076 ,  H04L1/1812 ,  H04L1/1861 ,  H04L5/0092 ,  H04W72/21 ,  H04L1/0026 ,  H04L1/1607 ,  H04L25/03343 ,  H04L2025/03426 ,  H04L2025/03802

摘要： A device capable of operating in a wireless communication environment. The device may be configured to determine a plurality of control signaling bits. The device may determine a plurality of cyclic redundancy check (CRC) bits based on the plurality of control signaling bits. The device may apply a channel coding scheme to the plurality of control signaling bits and the plurality of CRC bits. The plurality of CRC bits may be distributed among the plurality of control signaling bits prior to applying the channel coding scheme. The device may transmit the channel coded plurality of control signaling bits and CRC bits.

公开(公告)号：US20240356568A1

公开(公告)日：2024-10-24

申请号：US18574818

申请日：2021-06-30

申请人： NEC Laboratories Europe GmbH

发明人： Andres GARCIA SAAVEDRA ,  Xavier COSTA-PEREZ

IPC分类号： H03M13/00 ,  H03M13/11 ,  H03M13/29 ,  H03M13/35

CPC分类号： H03M13/6306 ,  H03M13/1128 ,  H03M13/2975 ,  H03M13/353

摘要： A method of operating a virtualized radio access point (vRAP) is provided. Transport blocks (TBs) are encoded/decoded by using iterative codes that exchange extrinsic information in each iteration. The exchanged extrinsic information is exploited to infer information about decodability of the data of the TBs.

公开(公告)号：US12107603B1

公开(公告)日：2024-10-01

申请号：US18049771

申请日：2022-10-26

申请人： Marvell Asia Pte Ltd

发明人： Nirmal Shende ,  Nedeljko Varnica

IPC分类号： H03M13/11 ,  G06N3/04 ,  G06F11/10 ,  G06N3/02 ,  G06N20/00 ,  H03M13/29 ,  H03M13/37 ,  H03M13/39 ,  H03M13/45 ,  H04L1/00

CPC分类号： H03M13/1108 ,  G06N3/04 ,  H03M13/1125 ,  G06F11/1068 ,  G06N3/02 ,  G06N20/00 ,  H03M13/1105 ,  H03M13/2948 ,  H03M13/3707 ,  H03M13/3746 ,  H03M13/3927 ,  H03M13/458 ,  H04L1/005

摘要： A method of reading data read from a NAND Flash memory device includes decoding a set of data read from the device, using an initial set of hard bit thresholds, when the decoding is unsuccessful, performing a read-retry operation that retries the decoding using, in order, each of a plurality of entries in a read-retry table of hard bit thresholds, stopping when decoding based on one of the entries is successful, and when the read-retry operation is unsuccessful, performing a deep retry operation using a set of log-likelihood ratios (LLRs) that vary in at least one of values or symmetries. NAND Flash memory apparatus includes a Flash media controller, a data bus, and an adaptive LLR engine configured to generate, for use in a deep retry operation, a set of LLRs that, and to transfer the set of LLRs that vary to the media controller via the bus.

公开(公告)号：US12099411B2

公开(公告)日：2024-09-24

申请号：US18169880

申请日：2023-02-16

申请人： SK hynix Inc.

发明人： Jin Ho Jeong ,  Hoiju Chung ,  Dae Suk Kim ,  Munseon Jang

IPC分类号： G06F11/10 ,  H03M13/29

CPC分类号： G06F11/1076 ,  H03M13/2927

摘要： An error processing circuit includes: a first H matrix calculation circuit configured to calculate a first H matrix and upstream data to generate a partial first parity, during an encoding operation; a second H matrix calculation circuit configured to calculate a second H matrix and the upstream data to generate a second parity, during the encoding operation; and a parity calculation circuit configured to sum the partial first parity and the second parity to generate a first parity, during the encoding operation.

公开(公告)号：US12095478B2

公开(公告)日：2024-09-17

申请号：US17877484

申请日：2022-07-29

申请人： SK hynix Inc.

发明人： Jin Ho Jeong ,  Dae Suk Kim ,  Munseon Jang

IPC分类号： H03M13/11 ,  H03M13/15 ,  G06F17/16 ,  G11C29/52 ,  H03M13/00 ,  H03M13/05 ,  H03M13/25 ,  H03M13/29

CPC分类号： H03M13/1177 ,  H03M13/1575 ,  H03M13/159 ,  G06F17/16 ,  G11C29/52 ,  H03M13/05 ,  H03M13/116 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/616

摘要： A memory includes a first check matrix calculation circuit suitable for generating a first parity by calculating a group indicator portion of a check matrix and a write data; a memory core suitable for storing the write data and the first parity; a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating the group indicator portion and the data which is read from the memory core; and a failure determination circuit suitable for accumulating the first syndromes for a region of the memory core to generate a vector and determining a presence of a failure of the region based on the vector.

公开(公告)号：US12047095B2

公开(公告)日：2024-07-23

申请号：US18314938

申请日：2023-05-10

申请人： Electronics and Telecommunications Research Institute

发明人： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Jae-Young Lee ,  Heung-Mook Kim

IPC分类号： H03M13/15 ,  H03M13/00 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29

CPC分类号： H03M13/152 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1165 ,  H03M13/271 ,  H03M13/2778 ,  H03M13/618 ,  H03M13/6362 ,  H03M13/253 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/6393 ,  H03M13/6552

摘要： A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

公开(公告)号：US12034535B2

公开(公告)日：2024-07-09

申请号：US18227527

申请日：2023-07-28

申请人： Panasonic Intellectual Property Corporation of America

发明人： Yutaka Murakami ,  Tomohiro Kimura ,  Mikihiro Ouchi

IPC分类号： H04L1/00 ,  H03M13/00 ,  H03M13/11 ,  H03M13/29

CPC分类号： H04L1/0068 ,  H03M13/1102 ,  H03M13/2906 ,  H03M13/616 ,  H03M13/6362 ,  H03M13/6516 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057

摘要： One coding method of a plurality of coding methods including at least a first coding method and a second coding method is selected, an information sequence is encoded by using the selected coding method, and an encoded sequence obtained by performing predetermined processing on the information sequence is modulated and transmitted. The first coding method is a coding method having a first coding rate, for generating a first encoded sequence by performing puncturing processing on a generated first codeword by using a first parity check matrix. The second coding method is a coding method having a second coding rate, for generating a second encoded sequence by performing puncturing processing on a generated second codeword by using a second parity check matrix that is different from the first parity check matrix, the second coding rate after the puncturing process being different from the first coding rate.

公开(公告)号：US20240220360A1

公开(公告)日：2024-07-04

申请号：US18369540

申请日：2023-09-18

申请人： Lodestar Licensing Group LLC

发明人： Aaron P. Boehm ,  Scott E. Schaefer

IPC分类号： G06F11/10 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4091 ,  H03M13/29

CPC分类号： G06F11/1068 ,  H03M13/2906 ,  G11C11/221 ,  G11C11/4087 ,  G11C11/4091

摘要： Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.

公开(公告)号：US12021616B2

公开(公告)日：2024-06-25

申请号：US18304029

申请日：2023-04-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Se-ho Myung ,  Kyung-joong Kim ,  Hong-sil Jeong

IPC分类号： H04L1/00 ,  H03M13/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/37

CPC分类号： H04L1/0041 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/2778 ,  H03M13/2906 ,  H03M13/3761 ,  H03M13/3769 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/152

摘要： A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to interleave the parity bits and group-wise interleave a plurality of parity bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern to perform parity permutation; a puncturer configured to puncture at least some of the group-wise interleaved parity bit groups; and an additional parity generator configured to select at least some of the punctured parity bit groups to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.

公开(公告)号：US20240195437A1

公开(公告)日：2024-06-13

申请号：US18079656

申请日：2022-12-12

申请人： Microsoft Technology Licensing, LLC

发明人： Amer Aref Hassan ,  David Anthony LICKORISH

IPC分类号： H03M13/29 ,  H04L1/00

CPC分类号： H03M13/2957 ,  H04L1/005

摘要： Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for an enhanced decoding system that utilizes a variable sequence decoding to demultiplex data streams at a receiver. For example, the receiver may utilize an erasures decoding when the number of unknown bits, such as dissimilar transmitted bits (e.g., ‘1 0’ or ‘0 1’), is below a threshold (which may be the Hamming distance D-1). Otherwise, if the number of dissimilar transmitted bits is above the threshold, a list decoding is utilized. If the list decoding does not produce a single result, but instead produces multiple possible results, selection logic may be employed. The selection logic may utilize an errors and erasures decoding of the possible results, a media decoding of the possible results, and/or the like.