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公开(公告)号：US12132499B2
公开(公告)日：2024-10-29
申请号：US18129948
申请日：2023-04-03
申请人： Dell Products L.P.
IPC分类号： H03M13/11
CPC分类号： H03M13/1108 , H03M13/1111 , H03M13/1151
摘要： A storage device syndrome-weight-based error correction system includes a syndrome-weight-based error correction subsystem coupled to a storage subsystem in a chassis. The syndrome-weight-based error correction subsystem performs a plurality of respective first error correction hard decoding operations on the storage subsystem that each utilize respective read voltage thresholds and that each generate a respective final codeword candidate having a respective syndrome weight. The syndrome-weight-based error correction subsystem identifies a first syndrome weight of a first final codeword candidate that was generated via the performance of one of the plurality of respective first error correction hard decoding operations that utilized first read voltage thresholds and that is lower than the syndrome weights of the final codeword candidates generated via the performance of the others of the plurality of respective first error correction hard decoding operations, and performs error correction soft decoding operations using the first read voltage thresholds.
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公开(公告)号：US20240356565A1
公开(公告)日：2024-10-24
申请号：US18643302
申请日：2024-04-23
发明人： Kangseok Lee , Bohwan Jun , Youngjun Hwang , Dongmin Shin
CPC分类号： H03M13/1174 , H03M13/1575 , H03M13/3746
摘要： An example operating method of an error correction code (ECC) circuit includes receiving a codeword from a memory device, calculating a syndrome vector based on the codeword and a parity-check matrix indicating whether messages are exchanged between check nodes and variable nodes, performing, when the syndrome vector is not a zero vector, sequential decoding on a plurality of columns of the parity-check matrix by decoding a first column in a first operation mode, the first column having a first variable node degree, decoding a second column in a second operation mode, the second column having a second variable node degree, and decoding a third column in a third operation mode, the third column having a third variable node degree, and calculating the syndrome vector whenever the sequential decoding of the plurality of columns is completed and iteratively performing the sequential decoding until the syndrome vector is the zero vector.
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公开(公告)号：US12126358B2
公开(公告)日：2024-10-22
申请号：US17815624
申请日：2022-07-28
发明人： Shih-Lien Linus Lu
CPC分类号： H03M13/1148 , G11C29/42 , G11C29/44 , H03M13/1174 , H03M13/1575 , H03M13/29
摘要： A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.
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公开(公告)号：US12126357B2
公开(公告)日：2024-10-22
申请号：US18085236
申请日：2022-12-20
申请人： SK hynix Inc.
发明人： Seon Woo Hwang , Seong Jin Kim , Jung Hwan Ji
CPC分类号： H03M13/1111 , H03M13/6356
摘要： In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.
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公开(公告)号：US12126356B2
公开(公告)日：2024-10-22
申请号：US18334905
申请日：2023-06-14
发明人： Yutaka Murakami
CPC分类号： H03M13/1102 , H03M13/23 , H03M13/235 , H03M13/2792 , H03M13/353 , H03M13/6502 , H03M13/6516 , H04L1/0041
摘要： A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.
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公开(公告)号：US12119075B2
公开(公告)日：2024-10-15
申请号：US18185198
申请日：2023-03-16
申请人： Kioxia Corporation
发明人： Avi Steiner , Ofir Kanter , Yasuhiko Kurosawa
IPC分类号： G06F11/10 , G06F11/07 , G06F11/30 , G06F13/16 , G06F13/28 , G11C29/02 , G11C29/52 , H03M13/11 , H03M13/15
CPC分类号： G11C29/52 , G11C29/022 , G11C29/024
摘要： Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.
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公开(公告)号：US12113546B2
公开(公告)日：2024-10-08
申请号：US18021037
申请日：2021-08-04
发明人： Qing Bian
IPC分类号： H03M13/11
CPC分类号： H03M13/1125 , H03M13/1151
摘要： A data processing method for use in a data processing device, a decoder, a network device and/or a computer-readable storage medium. The data processing method includes: classifying log likelihood ratio (LLR) elements according to a modulation mode, a preset decoder quantization threshold and a signal-to-noise ratio, to obtain a classification result; extracting feature information of each category in the classification result; calculating to obtain a scale factor according to the feature information of each category; and scaling the LLR elements according to the scale factor.
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公开(公告)号：US12112041B2
公开(公告)日：2024-10-08
申请号：US17950528
申请日：2022-09-22
申请人： SK hynix Inc.
发明人： Fan Zhang , Meysam Asadi , Haobo Wang
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0679 , H03M13/1108 , H03M13/1111 , H03M13/1128
摘要： Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.
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公开(公告)号：US12107601B2
公开(公告)日：2024-10-01
申请号：US17733165
申请日：2022-04-29
CPC分类号： H03M13/033 , G06N3/08 , H03M13/1102
摘要： A data error correction method, apparatus, device, and readable storage medium are disclosed. The method includes: acquiring target data to be error-corrected; performing error correction on the target data using an error-correcting code to obtain first data; judging whether the performing of the error correction on the target data is successful; responsive to the performing of the error correction on the target data being not successful, correcting the target data using a target neural network to obtain second data, determining the second data as the target data, and continuing to perform the error correction on the target data again; and responsive to the performing of the error correction on the target data being successful, determining the first data as the error-corrected target data.
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10.发明公开公开(公告)号：US20240322842A1
公开(公告)日：2024-09-26
申请号：US18735554
申请日：2024-06-06
发明人： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM
CPC分类号： H03M13/152 , H03M13/116 , H03M13/1162 , H03M13/1165 , H03M13/271 , H03M13/2778 , H03M13/618 , H03M13/6362 , H03M13/253 , H03M13/255 , H03M13/2906 , H03M13/6393 , H03M13/6552
摘要： A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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