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    Error detection and classification at a host device
    1.
    发明授权
    Error detection and classification at a host device 有权

    公开(公告)号：US12237844B2

    公开(公告)日：2025-02-25

    申请号：US17961805

    申请日：2022-10-07

    Applicant: Micron Technology, Inc.

    Inventor： Aaron P. Boehm ,  Scott E Schaefer

    IPC: H03M13/15 ,  H03M13/00 ,  H03M13/11

    Abstract: Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.

    Method and non-transitory computer-readable storage medium and apparatus for decoding low-density parity-check (LDPC) code
    2.
    发明授权
    Method and non-transitory computer-readable storage medium and apparatus for decoding low-density parity-check (LDPC) code 有权

    公开(公告)号：US12231146B2

    公开(公告)日：2025-02-18

    申请号：US18220464

    申请日：2023-07-11

    Applicant: Silicon Motion, Inc.

    Inventor： Duen-Yih Teng

    IPC: H03M13/11

    Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time. The non-sequential selection strategy indicates an arbitrary selection combination of the chunks in the codeword, which is different from that under the sequential selection strategy.

    Error correction method, error correction circuit and electronic device applying the same
    4.
    发明授权
    Error correction method, error correction circuit and electronic device applying the same 有权

    公开(公告)号：US12224768B2

    公开(公告)日：2025-02-11

    申请号：US18217892

    申请日：2023-07-03

    Applicant: ETRON TECHNOLOGY, INC.

    Inventor： Ho-Yin Chen ,  Han-Hsien Wang ,  Han-Nung Yeh

    IPC: H03M13/09 ,  H03M13/00 ,  H03M13/11

    Abstract: An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.

    SYNDROME DECODER CIRCUIT
    6.
    发明申请
    SYNDROME DECODER CIRCUIT 有权

    公开(公告)号：US20250038769A1

    公开(公告)日：2025-01-30

    申请号：US18358972

    申请日：2023-07-26

    Applicant: Winbond Electronics Corp.

    Inventor： Chuen-Der Lien ,  Chi-Shun Lin ,  Ngatik Cheung

    IPC: H03M13/15 ,  H03M13/11

    Abstract: The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X-1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.

    Method and apparatus for performing channel coding and decoding in communication or broadcasting system
    8.
    发明授权
    Method and apparatus for performing channel coding and decoding in communication or broadcasting system 有权

    公开(公告)号：US12191997B2

    公开(公告)日：2025-01-07

    申请号：US18519771

    申请日：2023-11-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyojin Lee ,  Taehyoung Kim ,  Sungjin Park ,  Jeongho Yeo

    IPC: H04L1/00 ,  H03M13/11 ,  H04L1/1812 ,  H04L5/00 ,  H04W72/23

    Abstract: Disclosed is a method performed by a user equipment (UE) in a communication system, including receiving, from a base station, downlink control information (DCI) including resource assignment information for a physical downlink shared channel (PDSCH); identifying a number of resource elements (REs) allocated for the PDSCH based on a number symbols for the PDSCH and a number of allocated physical resource blocks (PRBs), wherein a number of REs for a demodulation reference signal (DMRS) is excluded from the number of REs allocated for the PDSCH; identifying intermediate information based on the number of REs allocated for the PDSCH; identifying a transport block size (TBS) based on quantized intermediate information; and receiving, from the base station, the PDSCH based on the TBS.

    ENCODER AND ENCODING METHOD
    10.
    发明申请
    ENCODER AND ENCODING METHOD 有权

    公开(公告)号：US20240429943A1

    公开(公告)日：2024-12-26

    申请号：US18584838

    申请日：2024-02-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kijun Jeon ,  Kyoungbin Park ,  Minki Song ,  Dongmin Shin ,  Daeyeol Yang ,  Bohwan Jun ,  Youngjun Hwang

    IPC: H03M13/11 ,  H03M13/00

    Abstract: An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

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