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公开(公告)号：US11929762B2
公开(公告)日：2024-03-12
申请号：US17878431
申请日：2022-08-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Youngjun Hwang , Hongrak Son , Junho Shin , Bohwan Jun , Hyunseung Han
IPC: H03M13/11
CPC classification number: H03M13/1137 , H03M13/112 , H03M13/1134
Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
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公开(公告)号：US20240429943A1
公开(公告)日：2024-12-26
申请号：US18584838
申请日：2024-02-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kijun Jeon , Kyoungbin Park , Minki Song , Dongmin Shin , Daeyeol Yang , Bohwan Jun , Youngjun Hwang
Abstract: An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.
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公开(公告)号：US20240356565A1
公开(公告)日：2024-10-24
申请号：US18643302
申请日：2024-04-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kangseok Lee , Bohwan Jun , Youngjun Hwang , Dongmin Shin
CPC classification number: H03M13/1174 , H03M13/1575 , H03M13/3746
Abstract: An example operating method of an error correction code (ECC) circuit includes receiving a codeword from a memory device, calculating a syndrome vector based on the codeword and a parity-check matrix indicating whether messages are exchanged between check nodes and variable nodes, performing, when the syndrome vector is not a zero vector, sequential decoding on a plurality of columns of the parity-check matrix by decoding a first column in a first operation mode, the first column having a first variable node degree, decoding a second column in a second operation mode, the second column having a second variable node degree, and decoding a third column in a third operation mode, the third column having a third variable node degree, and calculating the syndrome vector whenever the sequential decoding of the plurality of columns is completed and iteratively performing the sequential decoding until the syndrome vector is the zero vector.
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公开(公告)号：US11249848B2
公开(公告)日：2022-02-15
申请号：US17134961
申请日：2020-12-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun Hwang , Hongrak Son , Dongmin Shin
Abstract: An error check code (ECC) decoder includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.
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公开(公告)号：US11664826B2
公开(公告)日：2023-05-30
申请号：US17478002
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kangseok Lee , Geunyeong Yu , Heeyoul Kwak , Hongrak Son , Dongmin Shin , Wijik Lee , Bohwan Jun , Youngjun Hwang
CPC classification number: H03M13/2948 , H03M13/096 , H03M13/1108 , H03M13/1575
Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.
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Patent Agency Ranking
公开(公告)号：US20230163785A1
公开(公告)日：2023-05-25
申请号：US17878431
申请日：2022-08-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Youngjun Hwang , Hongrak Son , Junho Shin , Bohwan Jun , Hyunseung Han
IPC: H03M13/11
CPC classification number: H03M13/1134 , H03M13/112
Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
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公开(公告)号：US11562803B2
公开(公告)日：2023-01-24
申请号：US17244195
申请日：2021-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun Hwang , Heeyoul Kwak , Bohwan Jun , Hongrak Son , Dongmin Shin , Geunyeong Yu
Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.
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公开(公告)号：US20240395352A1
公开(公告)日：2024-11-28
申请号：US18790881
申请日：2024-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Seonghyeog Choi , Hongrak Son , Youngjun Hwang
Abstract: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.
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公开(公告)号：US12119841B2
公开(公告)日：2024-10-15
申请号：US18141103
申请日：2023-04-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dae-Yeol Yang , Bohwan Jun , Hong Rak Son , Geunyeong Yu , Youngjun Hwang
CPC classification number: H03M13/1111 , H03M13/611
Abstract: a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.
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10.发明公开公开(公告)号：US20240128985A1
公开(公告)日：2024-04-18
申请号：US18242834
申请日：2023-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bohwan Jun , Daeyeol Yang , Hongrak Son , Geunyeong Yu , Youngjun Hwang
CPC classification number: H03M13/1105 , H03M13/6575
Abstract: A decoding device and a decoding method which relate to: receiving a codeword; estimating a number of errors included in the received codeword; and decoding the codeword based on the estimated number of errors using at least one of a first parity check matrix and a second parity check matrix, wherein the first parity check matrix corresponds to a first low-density parity check (LDPC) code, and the second parity check matrix corresponds to a second LDPC code, and wherein the first parity check matrix is based on a first code type, and the second parity check matrix is based on a second code type different from the first code type.
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