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    CIRCUITS AND METHODS FOR WRITING AND READING DATA
    3.
    发明申请
    CIRCUITS AND METHODS FOR WRITING AND READING DATA 审中-公开

    公开(公告)号：US20170346505A1

    公开(公告)日：2017-11-30

    申请号：US15602488

    申请日：2017-05-23

    申请人： Infineon Technologies AG

    发明人： Julie Henzler

    IPC分类号： H03M13/11 ,  H03M13/00

    CPC分类号： H03M13/11 ,  G06F11/00 ,  H03M13/09 ,  H03M13/096 ,  H03M13/13 ,  H03M13/19 ,  H03M13/611 ,  H03M13/63

    摘要： A writing circuit for writing write data into a memory comprises an evaluator configured for providing an error handling code on the basis of the write data. A modifier reversibly modifies extended write data comprising both the write data and the error handling code in dependence on address information related to a writing address in order to provide modified extended write data. A writer writes the modified extended write data in a position of the memory defined by a writing address. A reading circuit for reading extended read data from a memory comprises a reader configured for reading the extended read data from a position of the memory defined by a reading address. A de-modifier modifies the extended read data in dependence on address information related to a reading address in order to provide extracted read data and an extracted error handling code. An error-detector detects based on the extracted error handling code whether the extracted read data comprises an error.

    Methods and apparatuses utilizing check bit data generation
    4.
    发明授权
    Methods and apparatuses utilizing check bit data generation 有权
    利用校验位数据生成的方法和装置

    公开(公告)号：US09552252B2

    公开(公告)日：2017-01-24

    申请号：US14467983

    申请日：2014-08-25

    申请人： Seagate Technology LLC

    发明人： Jon D. Trantham ,  Brian T. Edgar ,  Mark Gaertner ,  Bruce Buch

    IPC分类号： H03M13/00 ,  G06F11/10 ,  H03M13/09

    CPC分类号： G06F11/1004 ,  G06F11/1012 ,  H03M13/09 ,  H03M13/096

    摘要： Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.

    摘要翻译： 本公开的某些示例性方面涉及其中逻辑电路基于从主机接收的用户数据生成错误检测码的方法和装置，并进一步产生要写入非易失性存储器的第一组校验位 通过将错误检测码与用户数据的散列数据地址组合在一起，与用户数据相结合。 在一些实施例中，与用户数据相关联的校验位提供用户数据被写入非易失性存储器电路的适当物理块地址中的验证。

    RECEIVING METHOD AND RECEIVER FOR SATELLITE-BASED AUTOMATIC IDENTIFICATION SYSTEMS
    5.
    发明申请
    RECEIVING METHOD AND RECEIVER FOR SATELLITE-BASED AUTOMATIC IDENTIFICATION SYSTEMS 审中-公开
    基于卫星自动识别系统的接收方法和接收机

    公开(公告)号：US20160380792A1

    公开(公告)日：2016-12-29

    申请号：US15110928

    申请日：2014-01-22

    申请人： EUROPEAN SPACE AGENCY

    发明人： Giulio Colavolpe ,  Alessandro Ugolini ,  Tommaso Foggi ,  Juan Lizarraga ,  Alberto Ginesi ,  Stefano Cioni

    IPC分类号： H04L27/227 ,  H03M13/09 ,  H04B7/185 ,  H04L1/00 ,  H04L7/00 ,  H04L27/00

    CPC分类号： H04L27/2275 ,  H03M13/09 ,  H03M13/096 ,  H03M13/1575 ,  H04B7/18513 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/0061 ,  H04L7/0029 ,  H04L7/007 ,  H04L27/0014 ,  H04L27/2332 ,  H04L2027/0028

    摘要： A method for demodulating a received signal relating to a sequence of transmitted symbols that have been modulated by continuous phase modulation includes normalizing samples of a sequence of samples generated from the received signal, to obtain a normalized sequence of samples, wherein an amplitude of each sample of the normalized sequence of samples has an absolute value equal to unity; estimating, on the basis of the normalized sequence of samples, a time offset and a frequency offset of the received signal, and using the estimated time offset and the estimated frequency offset for compensating the normalized sequence of samples for the time and frequency offsets, to obtain a compensated sequence of samples; and determining a sequence of symbols corresponding to the transmitted sequence of symbols on the basis of the compensated sequence of samples. Also disclosed is a receiver for demodulating a received signal relating to a sequence of transmitted symbols that have been modulated by continuous phase modulation.

    摘要翻译： 用于解调与通过连续相位调制调制的发送符号序列相关的接收信号的方法包括对从接收信号产生的采样序列的采样进行归一化，以获得标准化采样序列，其中每个采样的振幅 的样本的归一化序列具有等于1的绝对值; 基于归一化样本序列估计接收信号的时间偏移和频率偏移，并且使用估计的时间偏移和估计的频率偏移来补偿时间和频率偏移的标准化样本序列， 获得补偿的样本序列; 以及基于经补偿的样本序列来确定对应于所发送的符号序列的符号序列。 还公开了一种用于解调与通过连续相位调制调制的发射符号序列有关的接收信号的接收机。

    Preprocessing kernel print commands
    8.
    发明授权
    Preprocessing kernel print commands 有权
    预处理内核打印命令

    公开(公告)号：US09158513B2

    公开(公告)日：2015-10-13

    申请号：US14010737

    申请日：2013-08-27

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Janice M. Girouard ,  Yehuda Shiran

    IPC分类号： G06F9/45 ,  G06F11/36 ,  G06F9/44

    CPC分类号： G06F11/1004 ,  G06F3/1273 ,  G06F8/30 ,  G06F8/41 ,  G06F8/423 ,  G06F8/43 ,  G06F8/443 ,  G06F9/4486 ,  G06F11/3604 ,  H03M13/096

    摘要： Methods, apparatus and computer program products implement embodiments of the present invention that include replacing, in one or more initial source code files, each reference to a first function configured to convey system messages with a respective reference to a second function configured to convey the system messages, thereby producing respective corresponding preprocessed source code files for the one or more initial source code files. The respective corresponding preprocessed source code files are then compiled, thereby creating an executable file. While executing the executable file, a call to the second function is received, wherein the call includes a text string. A name of one of the respective corresponding preprocessed source code files storing the call to the second function is identified, and based on the identified name and the text string, a computed destination is determined for the text string. Finally, the text string is conveyed to the computed destination.

    摘要翻译： 方法，设备和计算机程序产品实现本发明的实施例，其包括在一个或多个初始源代码文件中替换每个引用以配置为传送系统消息的第一功能，该第一功能被配置为传送系统消息的第二功能 消息，从而为一个或多个初始源代码文件产生相应的相应的预处理源代码文件。 然后对相应的相应的预处理源代码文件进行编译，从而创建可执行文件。 在执行可执行文件时，接收到对第二功能的调用，其中呼叫包括文本串。 识别存储对第二功能的调用的相应的相应的预处理源代码文件之一的名称，并且基于所识别的名称和文本串，为文本串确定计算的目的地。 最后，文本串被传送到计算的目的地。

    BIT ALLOCATION OVER A SHARED BUS TO FACILITATE AN ERROR DETECTION OPTIMIZATION
    9.
    发明申请
    BIT ALLOCATION OVER A SHARED BUS TO FACILITATE AN ERROR DETECTION OPTIMIZATION 审中-公开
    通过共享总线对位分配进行更准确的错误检测优化

    公开(公告)号：US20150248373A1

    公开(公告)日：2015-09-03

    申请号：US14634106

    申请日：2015-02-27

    申请人： QUALCOMM Incorporated

    发明人： Shoichiro Sengoku

    IPC分类号： G06F13/42 ,  G06F11/22 ,  G06F11/16 ,  G06F11/30

    CPC分类号： G06F13/4291 ,  G06F11/1679 ,  G06F11/221 ,  G06F11/3027 ,  H03M13/096

    摘要： Various aspects directed towards facilitating an error detection optimization over a shared bus are disclosed. A master device is coupled to a slave device, and an encoded communication of a word is facilitated between the master device and the slave device via a control data bus. The encoded communication is encoded according to a protocol that allocates a plurality of least significant bits of the encoded communication to facilitate maximizing an error detection constant. The protocol allocates the plurality of least significant bits to include at least one additional error detection bit or at least a first most significant bit of a data portion of the word.

    摘要翻译： 公开了涉及促进共享总线上的错误检测优化的各个方面。 主设备耦合到从设备，并且经由控制数据总线在主设备和从设备之间促进字的编码通信。 编码通信根据分配编码通信的多个最低有效位的协议进行编码，以便最大化错误检测常数。 协议分配多个最低有效位以包括字的数据部分的至少一个附加错误检测位或至少第一最高有效位。

    FORMAT PRESERVING ENCRYPTION SYSTEMS FOR DATA STRINGS WITH CONSTRAINTS
    10.
    发明申请
    FORMAT PRESERVING ENCRYPTION SYSTEMS FOR DATA STRINGS WITH CONSTRAINTS 有权
    FORMAT保留用于具有约束的数据带的加密系统

    公开(公告)号：US20150134972A1

    公开(公告)日：2015-05-14

    申请号：US14598536

    申请日：2015-01-16

    申请人： Voltage Security, Inc.

    发明人： Luther W. Martin ,  Terence Spies ,  Matthew J. Pauker

    IPC分类号： G06F21/60

    CPC分类号： G06F21/602 ,  H03M13/096 ,  H04L9/0618 ,  H04L9/0643 ,  H04L2209/24 ,  H04L2209/56

    摘要： Format preserving encryption (FPE) cryptographic engines are provided for performing encryption and decryption on strings. A plaintext string may be converted to ciphertext by repeated application of a format preserving encryption cryptographic algorithm. Following each application of the format preserving cryptographic algorithm, the resulting version of the string may be analyzed to determine whether desired string constraints have been satisfied. If the string constraints have not been satisfied, further applications of the format preserving cryptographic algorithm may be performed. If the string constraints have been satisfied, the current version of the string may be used as an output for the cryptographic engine.

    摘要翻译： 提供格式保留加密（FPE）加密引擎，用于对字符串执行加密和解密。 可以通过重复应用格式保存加密密码算法将明文字符串转换为密文。 在每次应用格式保留加密算法之后，可以分析所得到的字符串版本，以确定是否满足期望的字符串约束。 如果字符串约束尚未得到满足，则可以执行格式保留加密算法的进一步应用。 如果字符串约束得到满足，则当前版本的字符串可能被用作加密引擎的输出。