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    NEURAL CORE, NEURAL PROCESSOR, AND DATA PROCESSING METHOD THEREOF
    3.
    发明公开
    NEURAL CORE, NEURAL PROCESSOR, AND DATA PROCESSING METHOD THEREOF 审中-公开

    公开(公告)号：US20240354572A1

    公开(公告)日：2024-10-24

    申请号：US18759661

    申请日：2024-06-28

    Applicant: Rebellions Inc.

    Inventor： Minhoo Kang ,  Wongyu Shin

    IPC: G06N3/08 ,  G06F3/06 ,  G06N3/063

    CPC classification number: G06N3/08 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06N3/063

    Abstract: A neural core, a neural processor, and a data processing method thereof are provided. The neural core includes a processing unit configured to generate output activation by performing calculation of input activation and a weight, a memory load/store unit configured to generate a memory calculation request requesting one-dimensional calculation of summing the output activation and target data, and a memory configured to receive the output activation and the memory calculation request, import the target data from a memory address in response to the memory calculation request, generate output data by performing the one-dimensional calculation of the target data and the output activation, and store the generated output data in the memory address.

    Serialized neural network computing unit
    5.
    发明授权
    Serialized neural network computing unit 有权

    公开(公告)号：US12124942B2

    公开(公告)日：2024-10-22

    申请号：US17109114

    申请日：2020-12-01

    Applicant: ANAFLASH INC.

    Inventor： Seung-Hwan Song

    IPC: G06N3/063 ,  G06F7/544 ,  G06N3/04 ,  G11C11/22 ,  G11C11/54

    CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N3/04 ,  G11C11/54 ,  G06F2207/4824 ,  G11C11/2293

    Abstract: A serialized neural network computing unit is disclosed. This computing unit comprises: a bit line; a memory array having a plurality of memory blocks, each memory block have one or more than one memory cells, each cell connected to the bit line; a control circuit configured to: apply a serialized input to the memory cells in a sequence such that outputs of the memory cells are produced in a sequence in response to the serialized input, wherein each of the outputs corresponds to a multiplication of the input and a weight value stored in the memory cell; and set a group of reference current levels, each having a specific current amount, for the control circuit to control the memory cells in generating respective output currents corresponding to the set of reference current levels.

    DYNAMIC VARIABLE BIT WIDTH NEURAL PROCESSOR
    8.
    发明公开
    DYNAMIC VARIABLE BIT WIDTH NEURAL PROCESSOR 审中-公开

    公开(公告)号：US20240338556A1

    公开(公告)日：2024-10-10

    申请号：US18743605

    申请日：2024-06-14

    Applicant: Apple Inc.

    Inventor： Paolo Di FEBBO ,  Waleed ABDULLA ,  Chaminda N. VIDANAGAMACHCHI ,  Yohan RAJAN

    IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

    CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/08

    Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

    METHOD AND APPARATUS FOR UTILIZING EXTERNAL NEURAL PROCESSOR FROM GRAPHICS PROCESSOR
    9.
    发明公开
    METHOD AND APPARATUS FOR UTILIZING EXTERNAL NEURAL PROCESSOR FROM GRAPHICS PROCESSOR 审中-公开

    公开(公告)号：US20240338555A1

    公开(公告)日：2024-10-10

    申请号：US18298029

    申请日：2023-04-10

    Applicant: QUALCOMM Incorporated

    Inventor： Elina KAMENETSKAYA ,  Amir MOMENI ,  Hamza OMAR ,  Engin IPEK ,  Alexei Vladimirovich BOURD ,  Zifeng LI

    IPC: G06N3/063

    CPC classification number: G06N3/063

    Abstract: Aspects of the disclosure are directed to concurrent tensor processing with multiple processing engines. In accordance with one aspect, an apparatus including a common memory unit; a first processing engine coupled to the common memory unit, wherein the first processing engine is configured to access a portion of an input tensor and a portion of a kernel tensor from the common memory unit; and a second processing engine coupled to the common memory unit, wherein the first processing engine is further configured to send the portion of the input tensor and the portion of the kernel tensor to the second processing engine and wherein the second processing engine is configured to generate a portion of an output tensor based on the portion of the input tensor and on the portion of the kernel tensor.

    HIERARCHICAL NETWORKS ON CHIP (NOC) FOR NEURAL NETWORK ACCELERATOR
    10.
    发明公开
    HIERARCHICAL NETWORKS ON CHIP (NOC) FOR NEURAL NETWORK ACCELERATOR 审中-公开

    公开(公告)号：US20240338339A1

    公开(公告)日：2024-10-10

    申请号：US18382938

    申请日：2023-10-23

    Applicant: MOFFETT INTERNATIONAL CO., LIMITED

    Inventor： Xiaoqian ZHANG ,  Zhibin XIAO

    IPC: G06F15/78 ,  G06N3/063

    CPC classification number: G06F15/7825 ,  G06N3/063

    Abstract: This application describes a hardware accelerator and a device for accelerating neural network computations. An example accelerator may include multiple cores and a central processing unit (CPU) respectively associated with DDRs, a data exchange interface connecting a host device to the accelerator, and a three-layer NoC architecture. The three-layer NoC architecture includes an outer-layer NoC configured to transfer data between the host device and the DDRs, a middle-layer NoC configured to transfer data among the plurality of cores; and an inner-layer NoC within each core and including a cross-bar network for broadcasting weights and activations of neural networks from a global buffer of the core to a plurality of processing entity (PE) clusters within the core.

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