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公开(公告)号:US12095555B2
公开(公告)日:2024-09-17
申请号:US18492140
申请日:2023-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung-Joong Kim , Seho Myung , Min Jang , Hong-Sil Jeong , Jae-Yoel Kim , Seok-Ki Ahn
CPC classification number: H04L1/0041 , H03M13/00 , H03M13/05 , H03M13/1102 , H03M13/116 , H03M13/1165 , H03M13/1177 , H03M13/25 , H03M13/256 , H03M13/616 , H03M13/6393 , H03M13/6513 , H04L1/00
Abstract: A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values.
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公开(公告)号:US12081236B2
公开(公告)日:2024-09-03
申请号:US18225841
申请日:2023-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Se-Ho Myung , Kyung-Joong Kim , Hong-Sil Jeong
CPC classification number: H03M13/1148 , H03M13/611 , H04L1/0057 , H04L1/0068 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/6356 , H03M13/6362 , H04L1/0041
Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.
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公开(公告)号:US12074703B2
公开(公告)日:2024-08-27
申请号:US18142720
申请日:2023-05-03
Inventor: Yutaka Murakami , Tomohiro Kimura , Mikihiro Ouchi
IPC: H03M13/00 , H03M13/25 , H04L1/00 , H04L1/06 , H04L27/34 , H03M13/11 , H04B7/0413 , H04B7/06 , H04L27/18
CPC classification number: H04L1/0041 , H03M13/255 , H04L1/0045 , H04L1/0057 , H04L1/0071 , H04L1/0643 , H04L27/34 , H03M13/1102 , H03M13/1165 , H04B7/0413 , H04B7/0669 , H04L2001/0093 , H04L27/18
Abstract: In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.
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公开(公告)号:US20240283592A1
公开(公告)日:2024-08-22
申请号:US18586414
申请日:2024-02-23
Inventor: Jong Ee OH , Min Ho CHEONG , Sok Kyu LEE
IPC: H04L5/00 , H03M13/11 , H03M13/23 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H04B7/04 , H04B7/06 , H04B7/08 , H04L1/00 , H04L1/06 , H04L27/18 , H04L27/26 , H04L27/34
CPC classification number: H04L5/0046 , H03M13/256 , H03M13/271 , H03M13/356 , H04B7/04 , H04B7/0697 , H04B7/08 , H04L1/0041 , H04L1/0057 , H04L1/06 , H04L1/0618 , H04L5/0026 , H04L27/186 , H04L27/2627 , H04L27/3416 , H03M13/1102 , H03M13/23 , H03M13/2957
Abstract: Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: deciding the number of bits (s) and encoders (NES) to allocate to one axis of a signal constellation; encoding an information bit based on the s and the NES and generating a coded block; parsing the coded block based on the s and the NES and generating a plurality of frequency sub-blocks; and transmitting the plurality of frequency sub-blocks to a receiver.
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公开(公告)号:US12068811B2
公开(公告)日:2024-08-20
申请号:US17819528
申请日:2022-08-12
Applicant: QUALCOMM Incorporated
Inventor: Wei Yang , Jing Jiang , Danlu Zhang , Gabi Sarkis , Runxin Wang , Hwan Joon Kwon , Krishna Kiran Mukkavilli , Tingfang Ji
IPC: H04B7/0413 , H03M13/11 , H04L1/00 , H04L5/00
CPC classification number: H04B7/0413 , H03M13/1102 , H04L1/0057 , H04L5/001 , H04L5/0046 , H04L5/0057 , H04L1/0003 , H04L1/0009
Abstract: A first device may select a base graph from a plurality of base graphs based on one or more of (a) a decoding complexity of a second device, (b) a device category of the second device, (c) a capability of the second device, (d) a decoder mode of the second device, (e) a receiver complexity of the second device, (f) a receiver mode of the second device, (g) a power consumption of the second device, (h) a power mode of the second device, or (i) an indication from the second device. The first device may output an LDPC coded transmission to the second device based on the selected base graph.
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公开(公告)号:US12068756B2
公开(公告)日:2024-08-20
申请号:US18325364
申请日:2023-05-30
Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
CPC classification number: H03M13/1102 , H03M13/116 , H03M13/2778 , H03M13/2903 , H03M13/618 , H03M13/152 , H03M13/253 , H03M13/255 , H03M13/2906
Abstract: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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公开(公告)号:US20240223308A1
公开(公告)日:2024-07-04
申请号:US18145844
申请日:2022-12-22
Applicant: QUALCOMM Incorporated
CPC classification number: H04L1/0063 , H03M13/1102 , H04L1/0057
Abstract: Methods, systems, and devices for wireless communications are described. A first wireless device, such as a wireless station (STA) or a wireless access point (AP), may perform a low-density parity check (LDPC) coding operation on input bits of a set of code blocks. Performing the LDPC coding operation on the input bits may produce a set of codewords including one or more codewords having a first codeword length and one or more codewords having a second, shorter codeword length. The first wireless device may arrange the set of codewords into a set of symbols such that a last symbol in time of the set of symbols includes the one or more codewords each having the second codeword length and no codewords having the first codeword length. The first wireless device may transmit, to a second wireless device, the plurality of symbols.
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公开(公告)号:US12009839B2
公开(公告)日:2024-06-11
申请号:US17810832
申请日:2022-07-05
Applicant: MAXLINEAR, INC.
Inventor: Rainer Strobel , Vladimir Oksman
IPC: H03M13/29 , H03M13/00 , H03M13/11 , H03M13/15 , H04L1/00 , H04L27/00 , H04L27/36 , H04L27/38 , H04L12/28
CPC classification number: H03M13/2906 , H03M13/1102 , H03M13/1515 , H03M13/152 , H04L1/0041 , H04L1/0057 , H04L27/36 , H04L27/38 , H04L12/2801
Abstract: A multi-carrier transmitter apparatus is disclosed. The apparatus includes an outer encoder, a shell mapper and an inner encoder. The outer encoder is configured to receive a signal, perform error correction using an outer code on the received signal and generate an outer encoder signal. The shell mapper is configured to perform constellation shaping on a subset of bits from the outer encoder signal and generate one or more constellation shaping bits. The inner encoder is configured to perform inner error correction/encoding using an inner code on a second subset of bits from the outer encoder signal and generate an inner correction signal.
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公开(公告)号:US20240162919A1
公开(公告)日:2024-05-16
申请号:US18414909
申请日:2024-01-17
Inventor: Yutaka MURAKAMI , Tomohiro Kimura , Mikihiro Ouchi
CPC classification number: H03M13/255 , H03M13/1102 , H03M13/1111 , H03M13/19 , H03M13/35 , H03M13/6362 , H04L1/00
Abstract: One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence.
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公开(公告)号:US11923872B2
公开(公告)日:2024-03-05
申请号:US18309278
申请日:2023-04-28
Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2757 , H03M13/1102 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/20 , H04L27/3416
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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