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公开(公告)号：US20240348267A1
公开(公告)日：2024-10-17
申请号：US18134690
申请日：2023-04-14
Applicant: Microsoft Technology Licensing, LLC
Inventor： Brett K. DODDS , Terry M. GRUNZKE
CPC classification number: H03M13/35 , H03M13/353 , H03M13/356 , H03M13/151 , H03M13/611
Abstract: A memory controller may receive memory data to be stored on a memory. A memory controller may receive metadata related to the memory data. The metadata may be selected from a predetermined list of metadata. A memory controller may identify an encoding polynomial of a plurality of polynomials that is associated with the metadata, each polynomial of the plurality of polynomials associated with different metadata from the predetermined list of metadata. A memory controller may generate a codeword using the encoding polynomial of the plurality of polynomials and the memory data.
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公开(公告)号：US11671520B2
公开(公告)日：2023-06-06
申请号：US17444248
申请日：2021-08-02
Applicant: Microchip Technology Incorporated
Inventor： Jason M. Sachs
CPC classification number: H04L69/28 , H03M13/25 , H03M13/35 , H03M13/373 , H04J3/067 , H04L63/123 , H04Q9/00 , G06F7/584 , H04L2463/121
Abstract: Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.
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公开(公告)号：US10014881B2
公开(公告)日：2018-07-03
申请号：US15363606
申请日：2016-11-29
Applicant: International Business Machines Corporation
Inventor： Mario Blaum , James L. Hafner , David A. Pease , Mohit Saxena , Mingyuan Xia
CPC classification number: H03M13/356 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1048 , G06F11/1076 , H03M13/154 , H03M13/2909 , H03M13/35 , H03M13/3707 , H03M13/373
Abstract: Embodiments relate to dynamically selecting an erasure code. State data is tracked to ascertain frequency of file access. One of at least two erasure codes are selected based on the tracked state data in order to lower data recovery cost. The erasure code may be selected as either a product code or a local reconstruction code. Each erasure code includes a mode that is either a fast code or a compact code. The fast code features a low recovery cost and the compact code features a low storage overhead for less frequently accessed data. Data is encoded with one of the selected erasure codes and one of the modes of the selected erasure code. Data blocks are dynamically converted between the fast and compact codes of the selected erasure code responsive to a workload change.
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公开(公告)号：US20180175967A1
公开(公告)日：2018-06-21
申请号：US15580538
申请日：2015-06-10
Applicant: LG ELECTRONICS INC.
Inventor： Kwangseok NOH , Hyunsoo KO , Dongkyu KIM , Sangrim LEE , Hojae LEE
CPC classification number: H04L1/001 , H03M13/09 , H03M13/1194 , H03M13/23 , H03M13/2739 , H03M13/2778 , H03M13/2906 , H03M13/2957 , H03M13/35 , H03M13/353 , H03M13/3938 , H03M13/6513 , H04L1/00 , H04L1/0009 , H04L1/0025 , H04L1/0041 , H04L1/0065 , H04L1/0068 , H04L1/0071 , H04L1/0075 , H04L1/16 , H04L1/1867 , H04W4/06 , H04W4/40
Abstract: The present invention relates to a method for performing channel encoding by a transmitting end in a wireless communication system. Particularly, the method comprises the steps of: transmitting, to a receiving end, a configuration indicating a plurality of channel coding configurations; performing channel encoding using a first channel coding configuration among the plurality of channel coding configurations; and performing reconfiguration from the first channel coding configuration to a second channel coding configuration according to a change in system requirements, wherein the plurality of channel coding configurations comprise channel coding configurations, each comprising at least one channel code concatenated differently according to the system requirements.
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公开(公告)号：US09985659B2
公开(公告)日：2018-05-29
申请号：US14810749
申请日：2015-07-28
Inventor： Jong Sun Park , Jang Won Park
CPC classification number: H03M13/35 , G06F11/1004 , G06F11/1048 , H03M13/05 , H03M13/152 , H03M13/1545 , H03M13/155 , H03M13/611
Abstract: A method for correcting error in a memory comprises setting a protected scope for at least part of unit data to be written in the memory according to an operation voltage of the memory; implementing error correction encoding for protected data corresponding to the protected scope among the unit data; and writing the unit data in the memory while matching them with parity data generated as a result of the error correction encoding.
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Patent Agency Ranking
公开(公告)号：US09927978B2
公开(公告)日：2018-03-27
申请号：US15444104
申请日：2017-02-27
Applicant: International Business Machines Corporation
Inventor： Kumar Abhijeet , Greg R. Dhuse , S. Christopher Gladwin , Gary W. Grube , Timothy W. Markison , Jason K. Resch
IPC: H04N7/173 , G06F3/06 , G06F11/10 , H03M13/15 , H03M13/00 , H04L9/14 , H04L9/08 , H04L29/06 , G06F21/10 , H04L29/08
CPC classification number: G06F3/0604 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/067 , G06F11/1076 , G06F21/10 , G06F2221/0755 , G06F2221/0784 , G06F2221/2107 , G06F2221/2151 , H03M13/1515 , H03M13/35 , H03M13/616 , H04L9/085 , H04L9/0869 , H04L9/0894 , H04L9/14 , H04L63/101 , H04L63/102 , H04L65/604 , H04L65/607 , H04L67/06 , H04L67/1097 , H04L2209/60 , H04N21/2181 , H04N21/23116 , H04N21/232
Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and to the memory, wherein the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations including to receive, via the interface, content retrieval messages for a data object. Then, based on the content retrieval messages for the data object and respectively for each associated data segment, the processing module determines respective groups of unique pillar combinations of at least read threshold number of EDSs, retrieves the respective groups of unique pillar combinations of at least read threshold number of EDSs from storage units (SUs) within the DSN, and provides the respective groups of unique pillar combinations of at least read threshold number of EDSs respectively to recipient device(s).
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公开(公告)号：US09921767B2
公开(公告)日：2018-03-20
申请号：US15373937
申请日：2016-12-09
Applicant: Western Digital Technologies, Inc.
Inventor： Martin Hassner , Satoshi Yamamoto
IPC: G11B5/09 , G06F3/06 , G11B20/18 , G11B20/10 , G06F11/07 , G06F11/10 , G11B20/12 , H03M13/35 , G11B5/596
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0676 , G06F11/0727 , G06F11/076 , G06F11/0793 , G06F11/1076 , G11B5/59627 , G11B20/10009 , G11B20/1217 , G11B20/1833 , G11B2020/1238 , G11B2020/1292 , H03M13/35
Abstract: To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage device is presented that performs a write process to store data on a storage medium of the data storage device responsive to one or more write operations received over a host interface. The data storage device monitors a quality of the write process and determines when the quality of the write process falls below a threshold quality. Responsive to the quality of the write process falling below the threshold quality, the data storage device indicates the quality of the write process to a data protection node for determination of data parity information that compensates for the quality of the write process, where the data parity information is provided by the data protection node for storage in a selected parity storage device.
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公开(公告)号：US09866241B2
公开(公告)日：2018-01-09
申请号：US15073034
申请日：2016-03-17
Applicant: SK Hynix Inc.
Inventor： Johnson Yen , Abhiram Prabhakar , Chung-Li Wang
CPC classification number: H03M13/1128 , H03M13/1111 , H03M13/1177 , H03M13/35 , H03M13/45 , H03M13/658
Abstract: Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits.
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公开(公告)号：US20170150184A1
公开(公告)日：2017-05-25
申请号：US15426183
申请日：2017-02-07
Inventor： Shinya KADONO , Makoto HAGAI
CPC classification number: H04N19/91 , H03M7/40 , H03M7/4006 , H03M7/42 , H03M13/07 , H03M13/35 , H04L65/607 , H04N19/103 , H04N19/13 , H04N19/132 , H04N19/146 , H04N19/157 , H04N19/172 , H04N19/174 , H04N19/176 , H04N19/184 , H04N19/46 , H04N19/61 , H04N19/70 , H04N21/6131
Abstract: A frame coding unit generates individual picture signal information from a moving picture signal, and outputs a frame code value which is a numeric value to be obtained as a result of coding picture signal information of each frame. A variable length coding unit decomposes the frame code value into unit frame code values which are basic units of coding, converts the unit frame code values into frame code words using only a single code table, and constructs a frame stream by combining the converted frame code words. A multiplexing unit multiplexes a header stream which is constructed through a method equivalent to a conventional method and the frame stream, and constructs a picture coded signal.
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公开(公告)号：US20170093428A1
公开(公告)日：2017-03-30
申请号：US15073034
申请日：2016-03-17
Applicant: SK Hynix Inc.
Inventor： Johnson Yen , Abhiram Prabhakar , Chung-Li Wang
CPC classification number: H03M13/1128 , H03M13/1111 , H03M13/1177 , H03M13/35 , H03M13/45 , H03M13/658
Abstract: Techniques are described for an adaptive low density parity check (LDPC) decoder. The techniques include receiving a first set of values corresponding to a first low density parity check codeword and noise, performing a first plurality of iterations of an iterative decoding algorithm using a first set of decoding parameters to decode the received first set of values, comparing a metric with a first threshold, and upon determining that the metric is larger than the threshold: selecting a second set of decoding parameters for the iterative LDPC decoder and performing a second plurality of iterations of the iterative LDPC decoding algorithm using the second set of decoding parameters to decode the received first set of values and generate a first set of decoded bits.
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