公开(公告)号：US20250061306A1

公开(公告)日：2025-02-20

申请号：US18931819

申请日：2024-10-30

Applicant: NANO DIMENSION TECHNOLOGIES, LTD.

Inventor： Eli DAVID ,  Eri RUBIN

IPC: G06N3/045 ,  G06F7/58 ,  G06N3/08

Abstract: A device, system, and method for approximating a neural network comprising N synapses or filters. The neural network may be partially-activated by iteratively executing a plurality of M partial pathways of the neural network to generate M partial outputs, wherein the M partial pathways respectively comprise M different continuous sequences of synapses or filters linking an input layer to an output layer. The M partial pathways may cumulatively span only a subset of the N synapses or filters such that a significant number of the remaining the N synapses or filters are not computed. The M partial outputs of the M partial pathways may be aggregated to generate an aggregated output approximating an output generated by fully-activating the neural network by executing a single instance of all N synapses or filters of the neural network. Training or prediction of the neural network may be performed based on the aggregated output.

公开(公告)号：US20250045021A1

公开(公告)日：2025-02-06

申请号：US18661437

申请日：2024-05-10

Applicant: Honeywell International Inc.

Inventor： James L. Tucker

IPC: G06F7/58

Abstract: Systems and methods for an active transistor RNG circuit with MEMS entropy are described herein. In one example, an RNG circuit includes one or more MEMS structures configured to provide an output, wherein the output includes active oscillations, charge, resistance, capacitance, and/or inductance values. The RNG circuit further includes active transistor RNG circuitry communicatively coupled to the one or more MEMS structures. The active transistor RNG circuitry is configured to generate a random number output based on the output by the one or more MEMS structures. The random number output generated by the active transistor RNG circuitry is an output of the RNG circuit.

公开(公告)号：US20250028675A1

公开(公告)日：2025-01-23

申请号：US18791963

申请日：2024-08-01

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  SELVAKUMAR PANNEER ,  SAURABH TANGRI ,  BEN ASHBAUGH ,  SCOTT JANUS ,  ABHISHEK APPU ,  VARGHESE GEORGE ,  RAVISHANKAR IYER ,  NILESH JAIN ,  PATTABHIRAMAN K ,  ALTUG KOKER ,  MIKE MACPHERSON ,  JOSH MASTRONARDE ,  ELMOUSTAPHA OULD-AHMED-VALL ,  JAYAKRISHNA P. S ,  ERIC SAMSON

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US12197629B2

公开(公告)日：2025-01-14

申请号：US17574670

申请日：2022-01-13

Applicant: Cortina Access, Inc.

Inventor： Ryan Patrick Donohue

IPC: G06F21/75 ,  G06F7/58 ,  G06F21/60 ,  G06F21/79

Abstract: A storage device and a data access method are provided. The storage device includes a primary storage unit and at least one additional unit. The primary storage unit includes: a primary memory element configured to store secret data and a primary access unit configured to receive an external access command. Each additional unit is configured to receive the external access command. Each additional unit includes: an additional memory element configured to store non-specific data, a local access generation element configured to trigger generating an internal access command based on the external access command, and an additional access unit configured to receive a local access command. The primary storage unit and each additional unit are coupled to a same power rail and a connection wire to simultaneously receive the external access command to parallelly (simultaneously) access the secret data and the non-specific data stored in each additional unit.

公开(公告)号：US12197234B2

公开(公告)日：2025-01-14

申请号：US17381385

申请日：2021-07-21

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young Il Kim ,  Seong Hee Park ,  Soon Yong Song ,  Geon Min Yeo ,  Il Woo Lee ,  Wun Cheol Jeong ,  Tae Wook Heo

IPC: G05D1/00 ,  B64C39/02 ,  B64D47/08 ,  G06F7/58 ,  G07C5/00 ,  G07C5/08 ,  H04R1/32 ,  H04W4/40 ,  B64U101/31

Abstract: A reconnaissance UAV and a surveillance flight method of the reconnaissance UAV which can reduce a number of required reconnaissance UAVs are provided. The surveillance flight method for detecting an unauthorized UAV includes: defining multiple flight passages in a UAV no-fly zone for a plurality of reconnaissance UAVs; controlling each of the plurality of reconnaissance UAVs to fly across adjacent flight passages at an interval by crossing a border of the adjacent flight passages; and controlling at least one of an image sensor and a noise sensor mounted on the reconnaissance UAV to dynamically change a direction detection thereof.

公开(公告)号：US12190231B2

公开(公告)日：2025-01-07

申请号：US15697035

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoo Jin Choi ,  Mostafa El-Khamy ,  Jungwon Lee

IPC: G06N3/08 ,  G06F7/58 ,  G06N3/047 ,  G06N3/063

Abstract: Apparatuses and methods of manufacturing same, systems, and methods for performing network parameter quantization in deep neural networks are described. In one aspect, multi-dimensional vectors representing network parameters are constructed from a trained neural network model. The multi-dimensional vectors are quantized to obtain shared quantized vectors as cluster centers, which are fine-tuned. The fine-tuned and shared quantized vectors/cluster centers are then encoded. Decoding reverses the process.

公开(公告)号：US20250004981A1

公开(公告)日：2025-01-02

申请号：US18793247

申请日：2024-08-02

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Lakshminarayana Striramassarma ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter ,  Prasoonkumar Surti ,  David Puffer ,  James Valerio ,  Ankur N. Shah

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

公开(公告)号：US12184437B2

公开(公告)日：2024-12-31

申请号：US18392043

申请日：2023-12-21

Applicant: BRIGHT DATA LTD.

Inventor： Derry Shribman ,  Ofer Vilenski

IPC: G06F7/58 ,  G06F8/71 ,  G06F9/455 ,  G06F9/48 ,  G06F16/955 ,  H04L9/40 ,  H04L12/28 ,  H04L12/46 ,  H04L47/283 ,  H04L61/256 ,  H04L61/2575 ,  H04L61/2585 ,  H04L61/2589 ,  H04L61/2592 ,  H04L61/4511 ,  H04L61/5007 ,  H04L67/01 ,  H04L67/02 ,  H04L67/025 ,  H04L67/133 ,  H04L67/141 ,  H04L67/142 ,  H04L67/288 ,  H04L67/2885 ,  H04L67/56 ,  H04L67/563 ,  H04L67/568 ,  H04L67/5681 ,  H04L67/63 ,  H04L69/16 ,  H04L69/167 ,  H04L69/168 ,  H04W4/80 ,  H04W48/18 ,  H04W84/10 ,  H04W84/18 ,  H04L101/69

Abstract: A method for fetching a content from a web server to a client device is disclosed, using tunnel devices serving as intermediate devices. The tunnel device is selected based on an attribute, such as IP Geolocation. A tunnel bank server stores a list of available tunnels that may be used, associated with values of various attribute types. The tunnel devices initiate communication with the tunnel bank server, and stays connected to it, for allowing a communication session initiated by the tunnel bank server. Upon receiving a request from a client to a content and for specific attribute types and values, a tunnel is selected by the tunnel bank server, and is used as a tunnel for retrieving the required content from the web server, using standard protocol such as SOCKS, WebSocket or HTTP Proxy. The client only communicates with a super proxy server that manages the content fetching scheme.

公开(公告)号：US12182262B2

公开(公告)日：2024-12-31

申请号：US17782746

申请日：2020-12-04

Applicant: EYL INC.

Inventor： Bu Suk Jeong ,  Dae Hyun Nam ,  Seong Joon Cho ,  Jung Hyun Baik ,  Tae Jin Lim

IPC: G06F21/55 ,  G06F7/58

Abstract: A random number generator resistant to side-channel attacks. The random number generator includes an entropy unit generating random pulses, a random frequency clock generator generating random frequencies by receiving random pulses output from the entropy unit, and an MCU externally masking a specific operation or a specific instruction based on a random frequency received from the random frequency clock generator.

公开(公告)号：US12182062B1

公开(公告)日：2024-12-31

申请号：US17961833

申请日：2022-10-07

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Joydeep Ray ,  Lakshminarayanan Striramassarma ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter ,  Prasoonkumar Surti ,  David Puffer ,  James Valerio ,  Ankur N. Shah

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.