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公开(公告)号：US20250069714A1
公开(公告)日：2025-02-27
申请号：US18919011
申请日：2024-10-17
Applicant: ILLUMINA, INC.
Inventor： Shile Zhang , Alex S. So , Shannon Kaplan , Kristina M. Kruglyak , Sven Bilke
IPC: G16H10/60 , C12Q1/6869 , C12Q1/6886 , G01N33/50 , G06F9/30 , G16B20/20 , G16B30/20
Abstract: Presented herein are techniques for determining microsatellite instability. The techniques include generating a reference sample dataset representative of or mimicing a hypothetical matched sample for an individual sample of interest. The reference sample dataset may be generated from a set of reference normal samples that are not matched to the sample of interest. For samples of interest lacking a matched sample, the reference sample dataset may be used to determine microsatellite instability and to provide an indication of a presence, absence, or degree of microsatellite instability of the sample of interest. The reference sample dataset may be generated such that individual microsatelliate regions associated with a high degree of variability between ethnic groups are filtered out, masked, or otherwise not considered.
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公开(公告)号：US20250068588A1
公开(公告)日：2025-02-27
申请号：US18822815
申请日：2024-09-03
Applicant: Intel Corporation
Inventor： Joydeep RAY , Aravindh ANANTARAMAN , Abhishek R. APPU , Altug KOKER , Elmoustapha OULD-AHMED-VALL , Valentin ANDREI , Subramaniam MAIYURAN , Nicolas GALOPPO VON BORRIES , Varghese GEORGE , Mike MACPHERSON , Ben ASHBAUGH , Murali RAMADOSS , Vikranth VEMULAPALLI , William SADLER , Jonathan PEARCE , Sungye KIM
Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20250068489A1
公开(公告)日：2025-02-27
申请号：US18724627
申请日：2022-08-30
Applicant: PAX COMPUTER TECHNOLOGY (SHENZHEN) CO., LTD.
Inventor： CHUNLEI ZHAO
Abstract: The present application is applicable to a field of computer technology, and provides a data processing method, a terminal device, and a storage medium. The data processing method comprises: invoking a library interface of a middle layer library by using an upper layer application; implementing a function corresponding to the library interface by invoking a bottom layer application programming interface by the middle layer library. The data processing method provided in the embodiment of the present application can reduce the difficulty of developing upper layer applications.
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公开(公告)号：US20250068473A1
公开(公告)日：2025-02-27
申请号：US18453867
申请日：2023-08-22
Applicant: Intel Corporation
Inventor： Jorge Eduardo Parra Osorio , Jiasheng Chen , Supratim Pal , James Valerio
Abstract: Described herein is a graphics processor comprising a graphics processing cluster coupled with the memory interface, the graphics processing cluster including a plurality of processing resources, a processing resource of the plurality of processing resources including a register file including a first plurality of registers associated with a first hardware thread of a plurality of hardware threads of the processing resource and a second plurality of registers associated with a second hardware thread of the plurality of hardware threads of the processing resource and first circuitry configured to facilitate access to memory on behalf of the plurality of hardware threads and store metadata for memory access requests from the plurality of hardware threads.
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公开(公告)号：US20250068425A1
公开(公告)日：2025-02-27
申请号：US18811392
申请日：2024-08-21
Applicant: Regents of the University of Minnesota
Inventor： John Mario Sartori , Shashank Ganapathi Hegde
Abstract: A system for Multi-Party Computation (MPC) includes a general-purpose programming language, an MPC processor, an MPC Instruction Set Architecture (ISA), and a compiler. The general-purpose programming language is used for writing an MPC application. The MPC processor executes the MPC application. The MPC ISA corresponds to the MPC processor. The compiler generates an intermediate representation for the MPC application and generates machine code for the intermediate representation by mapping and assembling MPC ISA instructions.
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Patent Agency Ranking
公开(公告)号：US20250068421A1
公开(公告)日：2025-02-27
申请号：US18908678
申请日：2024-10-07
Applicant: NVIDIA Corporation
Inventor： Maciej Piotr TYRLIK , Ajay Sudarshan TIRUMALA , Shirish GADRE , Frank Joseph EATON , Daniel Alan STIFFLER
Abstract: Various techniques for accelerating dynamic programming algorithms are provided. For example, a fused addition and comparison instruction, a three-operand comparison instruction, and a two-operand comparison instruction are used to accelerate a Needleman-Wunsch algorithm that determines an optimized global alignment of subsequences over two entire sequences. In another example, the fused addition and comparison instruction is used in an innermost loop of a Floyd-Warshall algorithm to reduce the number of instructions required to determine shortest paths between pairs of vertices in a graph. In another example, a two-way single instruction multiple data (SIMD) floating point variant of the three-operand comparison instruction is used to reduce the number of instructions required to determine the median of an array of floating point values.
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公开(公告)号：US12238217B2
公开(公告)日：2025-02-25
申请号：US18589125
申请日：2024-02-27
Applicant: Intel Corporation
Inventor： Jason W. Brandt
Abstract: Systems, methods, and apparatuses relating to circuitry to implement an instruction to create and/or use data that is restricted in how it can be used are described. In one embodiment, a hardware processor comprises a decoder of a core to decode a single instruction into a decoded single instruction, the single instruction comprising a first input operand of a handle including a ciphertext of an encryption key (e.g., cryptographic key), an authentication tag, and additional authentication data, and a second input operand of data encrypted with the encryption key, and an execution unit of the core to execute the decoded single instruction to: perform a first check of the authentication tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request of the core against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate the encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data, and the second check indicates the one or more restrictions are not violated, decrypt the data encrypted with the encryption key to generate unencrypted data, and provide the unencrypted data as a resultant of the single instruction.
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公开(公告)号：US12236237B2
公开(公告)日：2025-02-25
申请号：US18129808
申请日：2023-03-31
Applicant: Tenstorrent Inc.
Inventor： Davor Capalija , Ljubisa Bajic , Jasmina Vasiljevic , Yongbum Kim
Abstract: Processor cores using content object identifiers for routing and computation are disclosed. One method includes executing a complex computation using a set of processing cores. The method includes routing a set of content objects using a set of content object identifiers and executing a set of instructions. The set of instructions are defined using a set of operand identifiers. The operand identifiers represent content object identifiers in the set of content object identifiers. The content objects can be routed according to a named data networking (NDN) or content-centric networking (CCN) paradigm with the content object identifiers mentioned above serving as the names for the computation data being routed by the network.
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公开(公告)号：US20250063492A1
公开(公告)日：2025-02-20
申请号：US18940241
申请日：2024-11-07
Applicant: ECOLINK INTELLIGENT TECHNOLOGY, INC.
Inventor： Brandon Gruber
IPC: H04W52/02 , G06F1/3234 , G06F9/30
Abstract: A sensor is disabled when it receives a signal from a control unit that the control unit has been placed into one or more particular operating modes. In response to receiving the signal, the sensor becomes disabled, thereby preventing detection and/or transmission of certain signals to the security panel. When the control unit is placed into another mode of operation, the control unit sends a signal to the sensor and, in response, the sensor is re-enabled, allowing the sensor to function normally.
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公开(公告)号：US20250060992A1
公开(公告)日：2025-02-20
申请号：US18800365
申请日：2024-08-12
Applicant: Airbus SAS
Inventor： Sascha UHRIG , Johannes FREITAG
Abstract: A computing device comprising at least one processing module carrying multiple execution units each with a local memory unit; and a local network of the processing module linking at least some of the execution units to each other by respective communication paths; wherein the execution units are configured to execute a binary code segment at least temporarily stored in their respective associated local memory unit and derived from a computer executable program code application containing application code sections; and wherein at least one of the execution units is designated for executing a binary code segment as an assigned binary code segment based on a pre-determined runtime schedule with fixed time slots during which the execution unit is granted exclusive access to at least one of the communication paths when executing the assigned binary code segment in line with a pre-defined running order of the application code sections.
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