公开(公告)号：US20240362180A1

公开(公告)日：2024-10-31

申请号：US18647549

申请日：2024-04-26

申请人： Intel Corporation

发明人： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC分类号： G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Graphics processors and graphics processing units having dot product accumulate instructions for a hybrid floating point format are disclosed. In one embodiment, a graphics multiprocessor comprises an instruction unit to dispatch instructions and a processing resource coupled to the instruction unit. The processing resource is configured to receive a dot product accumulate instruction from the instruction unit and to process the dot product accumulate instruction using a bfloat16 number (BF16) format.

公开(公告)号：US20240354250A1

公开(公告)日：2024-10-24

申请号：US18507836

申请日：2023-11-13

申请人： METISX CO., LTD.

发明人： Do Hun KIM ,  Keebum Shin ,  Kwangsun Lee

IPC分类号： G06F12/0811

CPC分类号： G06F12/0811 ,  G06F9/30043

摘要： A multiprocessor system may include a plurality of processors including a first processor and a second processor; a first cache memory corresponding to the first processor; a second cache memory corresponding to the first processor and the second processor and storing a plurality of cache lines; and a controller manages data stored in the second cache memory. The second cache memory includes at least one first cache line in which data is written by the first processor and at least one second cache line in which data is written by the second processor. The controller: receives a command associated with a data update from the first processor, and in response to the command, sets the first cache line as a clean cache line or an invalidated cache line while not setting the second cache line as a clean cache line or an invalidated cache line.

公开(公告)号：US12118076B2

公开(公告)日：2024-10-15

申请号：US18130093

申请日：2023-04-03

申请人： Ventana Micro Systems Inc.

发明人： John G. Favor ,  Srivatsan Srinivasan

IPC分类号： G06F12/00 ,  G06F9/455 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0895 ,  G06F12/1045 ,  G06F12/14 ,  G06F21/52 ,  G06F21/55

CPC分类号： G06F21/52 ,  G06F9/45558 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0895 ,  G06F12/1054 ,  G06F12/1408 ,  G06F12/1458 ,  G06F21/556 ,  G06F2009/45583 ,  G06F2009/45587

摘要： A physically-tagged data cache memory mitigates side channel attacks by using a translation context (TC). With each entry allocation, control logic uses the received TC to perform the allocation, and with each access uses the received TC in a hit determination. The TC includes an address space identifier (ASID), virtual machine identifier (VMID), a privilege mode (PM) or translation regime (TR), or combination thereof. The TC is included in a tag of the allocated entry. Alternatively, or additionally, the TC is included in the set index to select a set of entries of the cache memory. Also, the TC may be hashed with address index bits to generate a small tag also included in the allocated entry used to generate an access early miss indication and way select.

公开(公告)号：US20240311302A1

公开(公告)日：2024-09-19

申请号：US18589852

申请日：2024-02-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jin Jung ,  Daehoon Kim ,  Hwanjun Lee ,  Jonggeon Lee ,  Jinin So

IPC分类号： G06F12/0811 ,  G06F12/084

CPC分类号： G06F12/0811 ,  G06F12/084

摘要： A processor includes a processing core configured to process each of a plurality of requests by accessing a corresponding one of a first memory and a second memory, a latency monitor configured to generate first latency information and second latency information, the first latency information comprising a first access latency to the first memory, and the second latency information comprising a second access latency to the second memory, a plurality of cache ways divided into a first partition and a second partition, and a decision engine configured to allocate each of the plurality of cache ways to one of the first partition and the second partition, based on the first latency information and the second latency information.

公开(公告)号：US12066975B2

公开(公告)日：2024-08-20

申请号：US17429291

申请日：2020-03-14

申请人： Intel Corporation

发明人： Altug Koker ,  Lakshminarayanan Striramassarma ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Sean Coleman ,  Varghese George ,  K Pattabhiraman ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  S Jayakrishna P ,  Prasoonkumar Surti

IPC分类号： G06F12/00 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

公开(公告)号：US12061547B2

公开(公告)日：2024-08-13

申请号：US17849634

申请日：2022-06-25

申请人： BANK OF AMERICA CORPORATION

发明人： Saurabh Arora ,  Sandeep Kumar Chauhan

IPC分类号： G06F12/0811 ,  G06F16/22 ,  G06F16/23

CPC分类号： G06F12/0811 ,  G06F16/2228 ,  G06F16/2365 ,  G06F2212/62

摘要： Embodiments of the invention are directed to systems, methods and computer program products structured for dynamic management of stored cache data based on usage information. The invention is structured for light-weight granular data caching based on construction of adapted hierarchical data objects with improved indexing, for reducing memory and processing burdens on data caching servers and reducing turnaround time for activity execution. Specifically, the invention is configured to trigger, via the proactive processor, retrieval of truncated technology data for caching from a usage database based on the adapted truncated cache data retrieval command; and construct a plurality of adapted hierarchical cache data objects, for each of the plurality of users, and cache the constructed plurality of adapted hierarchical cache data objects, for each of the plurality of users, in the distributed cache layer in a distributed cache layer.

公开(公告)号：US12050701B2

公开(公告)日：2024-07-30

申请号：US17833515

申请日：2022-06-06

申请人： Intel Corporation

发明人： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Michael LeMay ,  David M. Durham

IPC分类号： G06F21/60 ,  G06F9/30 ,  G06F9/32 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/14 ,  G06F21/12 ,  G06F21/62 ,  G06F21/72 ,  G06F21/79 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14

CPC分类号： G06F21/602 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30178 ,  G06F9/321 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0646 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1408 ,  G06F12/1458 ,  G06F12/1466 ,  G06F21/12 ,  G06F21/6227 ,  G06F21/72 ,  G06F21/79 ,  H04L9/0637 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/0869 ,  H04L9/0894 ,  H04L9/14 ,  G06F2009/45587 ,  G06F2212/1052 ,  H04L2209/125

摘要： Technologies disclosed herein provide cryptographic computing. An example method comprises executing a first instruction of a first software entity to receive a first input operand indicating a first key associated with a first memory compartment of a plurality of memory compartments stored in a first memory unit, and execute a cryptographic algorithm in a core of a processor to compute first encrypted contents based at least in part on the first key. Subsequent to computing the first encrypted contents in the core, the first encrypted contents are stored at a memory location in the first memory compartment of the first memory unit. More specific embodiments include, prior to storing the first encrypted contents at the memory location in the first memory compartment and subsequent to computing the first encrypted contents in the core, moving the first encrypted contents into a level one (L1) cache outside a boundary of the core.

公开(公告)号：US20240248856A1

公开(公告)日：2024-07-25

申请号：US18625675

申请日：2024-04-03

申请人： Microsoft Technology Licensing, LLC

发明人： Jordi MOLA

IPC分类号： G06F12/1045 ,  G06F11/34 ,  G06F12/0811

CPC分类号： G06F12/1045 ,  G06F11/3471 ,  G06F12/0811 ,  G06F2201/885

摘要： Compressing memory addresses within an execution trace via reference to a translation lookaside buffer (TLB) entry. A microprocessor identifies a TLB entry within a TLB slot, the TLB entry mapping a virtual memory page to a physical memory page. The microprocessor initiates logging of the TLB entry by initiating logging of at least a virtual address of the virtual memory page, and an identifier that uniquely identifies the TLB entry from among a plurality of live TLB entries. Subsequently, the microprocessor identifies a cache entry within a memory cache slot, the cache entry comprising a physical memory address corresponding to a cache line. The microprocessor initiates logging of the cache entry by matching a physical memory page identification portion of the physical memory address with the TLB entry, and then initiates logging of at least the identifier for the TLB entry and an offset portion.

公开(公告)号：US12045644B2

公开(公告)日：2024-07-23

申请号：US16882287

申请日：2020-05-22

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Abhijeet Ashok Chachad ,  David Matthew Thompson

IPC分类号： G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/121 ,  G06F13/16

CPC分类号： G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

摘要： A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.

公开(公告)号：US12038847B2

公开(公告)日：2024-07-16

申请号：US17952933

申请日：2022-09-26

申请人： Advanced Micro Devices, Inc.

发明人： William A. Moyes

IPC分类号： G06F12/1009 ,  G06F12/0811

CPC分类号： G06F12/1009 ,  G06F12/0811

摘要： A/D bit storage, processing, and mode management techniques through use of a dense A/D bit representation are described. In one example, a memory management unit employs an A/D bit representation generation module to generate the dense A/D bit representation. In an implementation, the A/D bit representation is stored adjacent to existing page table structures of the multilevel page table hierarchy. In another example, memory management unit supports use of modes as part of A/D bit storage.