公开(公告)号：US12130744B2

公开(公告)日：2024-10-29

申请号：US17672116

申请日：2022-02-15

Applicant: Mobileye Vision Technologies Ltd.

Inventor： Yosef Kreinin ,  Yosi Arbeli ,  Gil Israel Dogon

IPC: G06F9/30 ,  G06F7/00 ,  G06F9/345 ,  G06F9/38 ,  G06F9/52 ,  G06F11/10 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F15/78 ,  G06F15/80 ,  G06T1/20 ,  G06F12/0811

CPC classification number: G06F12/0875 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3865 ,  G06F9/3891 ,  G06F9/526 ,  G06F11/1008 ,  G06F12/084 ,  G06F12/0842 ,  G06F15/7867 ,  G06F15/80 ,  G06T1/20 ,  G06F12/0811 ,  G06F2212/452 ,  G06F2212/62

Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

公开(公告)号：US20240345990A1

公开(公告)日：2024-10-17

申请号：US18626775

申请日：2024-04-04

Applicant: Intel Corporation

Inventor： Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Varghese George ,  Ben Ashbaugh ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek Appu ,  Nicolas Galoppo Von Borries ,  Altug Koker ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Nilay Mistry ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Ankur Shah ,  Saurabh Tangri

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

公开(公告)号：US12118360B2

公开(公告)日：2024-10-15

申请号：US18093643

申请日：2023-01-05

Applicant: Ventana Micro Systems Inc.

Inventor： John G. Favor ,  Michael N. Michael

IPC: G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F12/0875 ,  G06F2212/452

Abstract: A microprocessor that includes a prediction unit (PRU) comprising a branch target buffer (BTB). Each BTB entry is associated with a fetch block (FBlk) (sequential set of instructions starting at a fetch address (FA)) having a length (no longer than a predetermined maximum length) and termination type. The termination type is from a list comprising: a sequential termination type indicating that a FA of a next FBlk in program order is sequential to a last instruction of the FBlk, and one or more non-sequential termination types. The PRU uses the FA of a current FBlk to generate a current BTB lookup value, looks up the current BTB lookup value, and in response to a miss, predicts the current FBlk has the predetermined maximum length and sequential termination type. An instruction fetch unit uses the current FA and predicted predetermined maximum length to fetch the current FBlk from an instruction cache.

公开(公告)号：US12117992B2

公开(公告)日：2024-10-15

申请号：US18114688

申请日：2023-02-27

Applicant: Ping Identity International, Inc.

Inventor： Dirk John Hogan

IPC: G06F16/23 ,  G06F12/0875 ,  G06F16/901 ,  G06Q10/105 ,  G06Q10/109 ,  G06Q10/067

CPC classification number: G06F16/2379 ,  G06F12/0875 ,  G06F16/9024 ,  G06Q10/105 ,  G06Q10/109 ,  G06F2212/1032 ,  G06Q10/067

Abstract: The technology disclosed relates to maintaining a cache of effective properties in an identity management system employing a graph. In particular, it relates to handling vertex/edge and/or graph topology updates in accordance with update notification requirements configured from a schema and, in conjunction with detecting updating of vertex/edge attributes and/or graph topology, recalculating effective attributes in accordance with the configured notification requirements.

公开(公告)号：US20240330203A1

公开(公告)日：2024-10-03

申请号：US18739768

申请日：2024-06-11

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: Devices and methods are provided for performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers. In an example, a device includes a processor that includes a multiply circuit. The multiply circuit is configured to multiply floating point numbers in response to a floating point multiply instruction, and is further configured to determine values of implied bits of mantissas of the floating point numbers, and multiply the mantissas in parallel with the determining operation.

公开(公告)号：US12105635B2

公开(公告)日：2024-10-01

申请号：US17384858

申请日：2021-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F9/30 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

公开(公告)号：US20240311149A1

公开(公告)日：2024-09-19

申请号：US18669104

申请日：2024-05-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/0875 ,  G06F15/78

CPC classification number: G06F9/3004 ,  G06F9/325 ,  G06F9/466 ,  G06F12/0815 ,  G06F12/0875 ,  G06F15/781

Abstract: Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

公开(公告)号：US12093534B2

公开(公告)日：2024-09-17

申请号：US17932309

申请日：2022-09-15

Applicant: RayMX Microelectronics, Corp.

Inventor： Yinghui Fu ,  Yunlu Zhang ,  Hao Li

IPC: G06F3/06 ,  G06F12/0875

CPC classification number: G06F3/0619 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F12/0875 ,  G06F2212/1032

Abstract: Disclosed are a method for inheriting a defect block table and a storage device thereof. The method applied to a controller of a storage device includes the steps of: storing an original defect block table in a first storage location of a storage module of the storage device, wherein the original defect block table records defect block information of each plane of the storage module; and in response to a low-level format operation being performed on the storage device, reading the original defect block table, and executing a adaptive inheritance procedure based on a multi-plane mode in which the storage device operates, to generate and store a system defect block table in a second storage location of the storage module, wherein the system defect block table records defect block information corresponding to the multi-plane mode.

公开(公告)号：US12086067B2

公开(公告)日：2024-09-10

申请号：US18141463

申请日：2023-04-30

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F12/0855 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/0855 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems and methods are disclosed for load-store pipeline selection for vectors. For example, an integrated circuit (e.g., a processor) for executing instructions includes an L1 cache that provides an interface to a memory system; an L2 cache connected to the L1 cache that implements a cache coherency protocol with the L1 cache; a first store unit configured to write data to the memory system via the L1 cache; a second store unit configured to bypass the L1 cache and write data to the memory system via the L2 cache; and a store pipeline selection circuitry configured to: identify an address associated with a first beat of a store instruction with a vector argument; select between the first store unit and the second store unit based on the address associated with the first beat of the store instruction; and dispatch the store instruction to the selected store unit.

公开(公告)号：US12079470B2

公开(公告)日：2024-09-03

申请号：US17379345

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew Pierson

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/14

CPC classification number: G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/14 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/60

Abstract: Disclosed embodiments relate to one or more techniques to control access by a requestor of a computing system to a shared memory resource. In one embodiment, a technique includes determining a number (N) of pending requests to be sent to the memory by the requestor, determining a number (M) of requests that the requestor is limited to sending based on an amount of buffering resources available, and comparing M to N. When N is both greater than zero and less than or equal to M, the requestor sends the N pending requests to the memory. When N is both greater than zero and greater than M, M is compared to a hysteresis value (R) and, when M is less than R, the requestor sends R of the N pending requests to the memory.