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    INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR MULTIPLE-PRECISION MULTIPLY-AND-ACCUMULATE OPERATION
    2.
    发明公开
    INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR MULTIPLE-PRECISION MULTIPLY-AND-ACCUMULATE OPERATION 审中-公开

    公开(公告)号：US20240338178A1

    公开(公告)日：2024-10-10

    申请号：US18298315

    申请日：2023-04-10

    申请人： EDGECORTIX INC

    发明人： Anudeep CHERLAPALLY ,  Nikolay NEZ ,  Antonio Tomas Nevado VILCHEZ

    IPC分类号： G06F7/544 ,  G06F7/498 ,  G06F7/499

    CPC分类号： G06F7/5443 ,  G06F7/4983 ,  G06F7/49915

    摘要： Multiple-precision multiply-and-accumulate operation is performed by a multiply-and-accumulate (MAC) unit configured to operate in an integer mode to perform computations on first data-width integer values to produce third data-width integer values and configured to operate in a floating point mode to perform computations on second data-width floating point values to produce third data-width floating point values, wherein the second data width is twice the first data width and the third data width is larger than the second data width. The MAC unit includes a first multiplier configured to multiply two integer values in the integer mode or multiply mantissa values extracted from each of two floating point values in the floating point mode. The MAC unit further includes a second multiplier, and is further configured to multiply two integer values in the integer mode or refrain from using the second multiplier in the floating point mode.

    Processing Unit
    3.
    发明公开
    Processing Unit 审中-公开

    公开(公告)号：US20240296010A1

    公开(公告)日：2024-09-05

    申请号：US18591349

    申请日：2024-02-29

    申请人： Graphcore Limited

    发明人： Thomas BROWN

    IPC分类号： G06F7/499 ,  G06F7/523 ,  G06F7/556

    CPC分类号： G06F7/49915 ,  G06F7/523 ,  G06F7/556

    摘要： A processing unit is provided with circuitry enabling execution quick evaluation of an exponential function. A multiplier circuit is used to multiply the input operand by log2(e), such that a result for the exponential function may be determined by evaluating 2i+f, where i is an integer part of a fixed-point number and f is a fractional part of the fixed-point number. A lookup table is used for providing an estimate for 2f based on the l MSBs of f. The lookup entries are provided according to a function such that the estimates for 2f are provided without bias towards either zero or infinity in the result. In other words, the maximum multiplicative error for each entry of the lookup table is the same in both negative and positive directions. In this way, statistical errors in the evaluation of a large number of exponential functions may be avoided.

    Control signaling design for improved resource utilization
    5.
    发明授权
    Control signaling design for improved resource utilization 有权

    公开(公告)号：US12058714B2

    公开(公告)日：2024-08-06

    申请号：US18153997

    申请日：2023-01-12

    申请人： Samsung Electronics Co., Ltd.

    发明人： Aris Papasakellariou

    IPC分类号： H04W72/21 ,  G06F7/499 ,  H04W72/0453 ,  H04W72/23 ,  H04W72/50 ,  H04W72/53 ,  H04W72/54

    CPC分类号： H04W72/535 ,  G06F7/49973 ,  H04W72/0453 ,  H04W72/21 ,  H04W72/23 ,  H04W72/53 ,  H04W72/54

    摘要： Methods and apparatuses for PDCCH reception and transmission. A method for PDCCH reception includes transmitting a capability for receptions of PDCCHs on a downlink (DL) cell. PDCCH receptions on the DL cell are according to (X1, Y1) or (X2, Y2) when any two PDCCH receptions are within Y1 or Y2 symbols or have first symbols separated by at least X1 or X2 symbols, respectively. The method further includes receiving a configuration of search space sets for PDCCH receptions on the DL cell; determining, based on the configuration of the search space sets, whether PDCCH receptions are according to (X2, Y2); and receiving on the DL cell: a maximum number of MPDCCHmax,X1,μ PDCCHs within Y1 symbols when PDCCH receptions are not according to (X2, Y2), and a maximum number of MPDCCHmax,X2,μ PDCCHs within Y2 symbols when PDCCH receptions are according to (X2, Y2).

    SOFTMAX AND LOG SOFTMAX METHOD AND SYSTEM
    9.
    发明公开
    SOFTMAX AND LOG SOFTMAX METHOD AND SYSTEM 审中-公开

    公开(公告)号：US20240061903A1

    公开(公告)日：2024-02-22

    申请号：US17892852

    申请日：2022-08-22

    申请人： Xilinx, Inc.

    发明人： Wenzong Yang ,  Wang Xi ,  Yadong Li ,  Junbin Wang ,  Shaoxia Fang

    IPC分类号： G06F17/16 ,  G06F7/544 ,  G06F7/552 ,  G06F7/499

    CPC分类号： G06F17/16 ,  G06F7/5443 ,  G06F7/552 ,  G06F7/4991

    摘要： Circuits and methods for determining a maximum bias for computing softmax on a tensor include a processor circuit configured to transform in parallel, elements of each group of a plurality of groups of elements of a tensor X into respective power-of-two elements. The respective power-of-two element from element xt of the tensor is pt, pt=(xt*log2e), and pt has an integer part and a fraction part. A first comparison circuit (204) is configured to determine respective group-level biases for the groups. The group-level bias of groupm is dm, and dm is an integer part of a maximum of the power-of-two elements of groupm. A second comparison circuit is configured to determine a greatest one of the respective group-level biases to be a tensor-level bias, dmax.

    Look Ahead Normaliser
    10.
    发明公开
    Look Ahead Normaliser 审中-公开

    公开(公告)号：US20240012613A1

    公开(公告)日：2024-01-11

    申请号：US18372737

    申请日：2023-09-26

    申请人： Imagination Technologies Limited

    发明人： Casper Van Benthem

    IPC分类号： G06F5/01 ,  G06F7/499

    CPC分类号： G06F5/01 ,  G06F7/49936

    摘要： Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.