公开(公告)号：US20250053611A1

公开(公告)日：2025-02-13

申请号：US18402810

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Win-San Khwa ,  Yi-Lun Lu ,  Jen-Chieh Liu ,  Jui-Jen Wu ,  Meng-Fan Chang

IPC: G06F17/16 ,  G06F5/01 ,  G06F17/15

Abstract: Embodiment described herein provide systems, apparatuses and methods for convoluting a filter (“kernel”) to input data in the form of an input array by reusing computations of repeated data entries in the input array due to convolution movements from one convolution step to the next. In one embodiment, to compute a convolution of an input matrix and a filter matrix, instead of unrolling data entries from the input matrix of each convolution step into an input vector, only non-repeated new data entries at each convolution step may be added to the input vector. An input mapping circuit that implements an input parameter mapping matrix may then iteratively map data entries of the input vector to different weight registers that corresponds to weights in the filter matrix.

公开(公告)号：US20250036358A1

公开(公告)日：2025-01-30

申请号：US18358586

申请日：2023-07-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William Gerald O'FARRELL ,  Christopher ANAND ,  James YOU ,  Lucas DUTTON ,  Steven GONDER ,  Felix FONG ,  Silvia Melitta MUELLER

IPC: G06F5/01 ,  G06F7/50 ,  G06F7/523 ,  G06F7/76

Abstract: A multi-operation computer instruction is executed to obtain an intermediate result. The execution includes selecting digits of a plurality of digits of multiple values to be multiplied. A location defined to hold a digit is greater in size than the size of the digit and further defined to hold a carry digit. The digits are selected from a predefined group of digits of a plurality of predefined groups based on a selection control of the instruction. The digits selected are multiplied to obtain a plurality of results. At least one result may be shifted a preselected amount to obtain at least one shifted result. One or more results and any shifted results, at least, are added to obtain an intermediate result. Execution of the instruction is repeated for multiple other predefined groups providing a plurality of intermediate results used to obtain a product of multiplying the multiple values.

公开(公告)号：US20250021307A1

公开(公告)日：2025-01-16

申请号：US18896829

申请日：2024-09-25

Applicant: PUFsecurity Corporation

Inventor： Wen-Ching Lin

IPC: G06F7/72 ,  G06F5/01 ,  G06F7/505 ,  G06F7/523 ,  G06F7/535

Abstract: A modular operation device for handling a modular multiplication, comprises a controller, configured to divide a multiplicand into a plurality of multiplicand words, a multiplier into a plurality of multiplier words, and a modulus into a plurality of modulus words; a first plurality of processing elements, coupled to the controller, configured to compute a first plurality of updated carry results and a first plurality of updated sum results; a second plurality of processing elements, coupled to the controller, configured to compute a second plurality of updated carry results and a second plurality of updated sum results; and a reduction element, coupled to the controller, configured to compute a resulting remainder according to the second plurality of updated carry results and the second plurality of updated sum results.

公开(公告)号：US12182533B2

公开(公告)日：2024-12-31

申请号：US17100748

申请日：2020-11-20

Applicant: MENTIUM TECHNOLOGIES INC.

Inventor： Farnood Merrikh Bayat

IPC: G06F7/544 ,  G06F1/3234 ,  G06F1/329 ,  G06F5/01 ,  G06F7/499 ,  G06F7/50 ,  G06F7/523 ,  G06F7/74 ,  G06F9/50

Abstract: A method includes obtaining input data and separating the input data into a first subset of input data and a second subset of input data, the first subset of input data including positive input data and the second subset of input data including negative input data. The method includes performing positive computations on the first subset of input data to determine one or more first results and performing negative computations on the second subset of input data to determine one or more second results. The method includes aggregating the one or more first results and the one or more second results to determine a solution based on the aggregating. The method includes executing an application using a machine learning model or a deep neural network based on the determined solution.

公开(公告)号：US12182063B2

公开(公告)日：2024-12-31

申请号：US18401571

申请日：2023-12-31

Applicant: Cornami, Inc.

Inventor： Raymond J. Andraka

IPC: G06F5/01 ,  G06F7/487 ,  G06F7/50 ,  G06F7/52 ,  G06F7/523 ,  G06F7/544 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80 ,  H03K19/21

Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

公开(公告)号：US12169534B2

公开(公告)日：2024-12-17

申请号：US17113898

申请日：2020-12-07

Applicant: International Business Machines Corporation

Inventor： Malte Johannes Rasch

IPC: G06F17/16 ,  G06F5/01 ,  G06N3/065 ,  G06N3/08

Abstract: Techniques for noise and bound management for DNN training on RPU crossbar arrays using a scaling factor based on a worst-case scenario are provided. In one aspect, a method for noise and bound management includes: obtaining input vector values x for an analog crossbar array of RPU devices, wherein a weight matrix is mapped to the analog crossbar array of RPU devices; and scaling the input vector values x based on a worst-case scenario to provide scaled input vector values x′ to use as input to the analog crossbar array of RPU devices, wherein the worst-case scenario includes an assumed maximal weight of the weight matrix multiplied by a sum of absolute values from the input vector values x.

公开(公告)号：US12159437B2

公开(公告)日：2024-12-03

申请号：US17810509

申请日：2022-07-01

Applicant: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.

Inventor： Fuzheng Yang ,  Zexing Sun ,  Lihui Yang ,  Shuai Wan

IPC: G06T9/00 ,  G06F5/01 ,  G06F7/24

Abstract: Disclosed are a partitioning method, an encoder, a decoder and a computer storage medium. The method includes: determining location information of a point of a point cloud to be partitioned; when i is less than or equal to M−1, determining right-shift number Ni of ith LOD layer in the point cloud, M representing a preset maximum quantity of layers for LOD partitioning; for the ith LOD layer, shifting location information of the point rightwards by Ni-digit, performing storing in a preset storage area based on right-shifted location information; determining location information of a parent point corresponding to a current point in the ith LOD layer; according to determined location information of the parent point, searching the preset storage area for a neighbor point of the parent point; partitioning the current point into an (i+1)th LOD layer, or the neighbor point into the ith LOD layer.

公开(公告)号：US20240370227A1

公开(公告)日：2024-11-07

申请号：US18774303

申请日：2024-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Sukhan LEE

IPC: G06F7/487 ,  G06F5/01 ,  G06F7/544 ,  G06F9/30

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

公开(公告)号：US20240354056A1

公开(公告)日：2024-10-24

申请号：US18305869

申请日：2023-04-24

Applicant: STMicroelectronics International N.V.

Inventor： Pierre Gobin ,  Jeremy Ribeiro De Freitas

IPC: G06F7/485 ,  G06F5/01 ,  G06F7/556

CPC classification number: G06F7/485 ,  G06F5/012 ,  G06F7/556

Abstract: A circuit for computing sine and cosine of an angle iteratively includes: a counter; an angle updating circuit configured to compute, for each iteration, an updated value of the angle; and a coordinate updating circuit including: a first register for storing a cosine value; a second register for storing a sine value; and a first custom floating-point adder/subtractor (CFPAS) circuit and a second CFPAS circuit having a same structure, where an output of the first register and an output of the second register are coupled to a first input terminal and a second input terminal of the first CFPAS circuit, and are coupled to a second input terminal and a first input terminal of the second CFPAS circuit, where an output of the counter is coupled to a third input terminal of the first CFPAS circuit and a third input terminal of the second CFPAS circuit.

公开(公告)号：US20240333960A1

公开(公告)日：2024-10-03

申请号：US18732576

申请日：2024-06-03

Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.

Inventor： Xiaoyu XIU ,  Yi-Wen CHEN ,  Xianglin WANG

IPC: H04N19/513 ,  G06F5/01 ,  H04N19/107 ,  H04N19/132 ,  H04N19/139 ,  H04N19/159 ,  H04N19/176 ,  H04N19/189 ,  H04N19/423 ,  H04N19/54

CPC classification number: H04N19/513 ,  G06F5/01 ,  H04N19/107 ,  H04N19/132 ,  H04N19/139 ,  H04N19/159 ,  H04N19/176 ,  H04N19/189 ,  H04N19/423 ,  H04N19/54

Abstract: A method for video coding is provided, including: providing a motion vector (MV) rounding process that is configured to perform a MV rounding operation; applying the MV rounding process to at least a first MV used in a first prediction tool selected from a first set of tools including: pair-wise merge candidate, triangle prediction mode, and affine mode; and applying the MV rounding process to at least a second MV used in a second prediction tool selected from a second set of tools including: temporal motion vector prediction (TMVP), alternative temporal motion vector prediction (ATMVP), and merge mode with motion vector differences (MMVD).