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公开(公告)号：US12113994B2
公开(公告)日：2024-10-08
申请号：US17674246
申请日：2022-02-17
Applicant: V-NOVA INTERNATIONAL LIMITED
Inventor： Richard Clucas
Abstract: A video decoder chipset comprises a video decoder function, an upscaler function and a combiner function. The video decoder function is configured to (i) decode encoded video data to generate decoded video data at a first level of quality, the encoded video data having been derived by an encoder using first video data at a second, higher level of quality and (ii) output the decoded video data for storage in a memory. The upscaler function is configured to (i) obtain the decoded video data from the memory and (ii) upscale the obtained decoded video data to generate second video data at the second level of quality. The combiner function is configured to (i) obtain residual data, the residual data having been derived by the encoder based on the first video data and the second video data, (ii) combine the second video data with the residual data to generate enhanced video data, and (iii) output the enhanced video data.
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公开(公告)号：US20240264801A1
公开(公告)日：2024-08-08
申请号：US18106274
申请日：2023-02-06
Applicant: Arm Limited
Inventor： Brendan James MORAN , Michael BARTLING , Andreas Lars SANDBERG
Abstract: A 1-hot path signature accelerator includes a register, first and second accumulator, and an outer product circuit. The register stores an input frame, where the input frame has, at most, one bit of each element set. The first accumulator calculates a present summation by adding the input frame to a previous sum of previous input frames inputted to the 1-hot path signature accelerator within a timeframe. The outer product circuit receives each element of the present summation from the first accumulator and each element of the input frame stored in the register to output a present outer product. Since the input frame has at most one bit of each element set, the outer product circuit is reduced to a logical operation. The second accumulator outputs a present second-layer summation by adding the present outer product to a previous second-layer sum of outputs from the outer product circuit within the timeframe.
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公开(公告)号：US20240192924A1
公开(公告)日：2024-06-13
申请号：US18503494
申请日：2023-11-07
Applicant: NXP B.V.
Inventor： Alexandre Venelli , Francois Dassance
Abstract: Shuffling and sliding subgroup techniques are provided to shuffle an order of a plurality of data blocks. The techniques include selecting a first value for a starting position and a second value for a step size. A first iteration of the technique includes generating a first subgroup to include a first subset of the plurality of data blocks based on the first value and the second value and executing data operations associated therewith. Then, in each of one or more subsequent iterations based on whether all of the data blocks have been added to the shuffled order, subsequent subgroups are added to the shuffled order that each include a different subset of the plurality of data blocks that are shifted by one position from data blocks in the previously generated subgroup and executing data operations associated therewith.
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公开(公告)号：US20240176590A1
公开(公告)日：2024-05-30
申请号：US18522797
申请日：2023-11-29
Inventor： Jin-Ho HAN
CPC classification number: G06F7/5443 , G06F5/01 , G06F7/483
Abstract: An embodiment of the present disclosure may provide a multiply-accumulate operation method performed by a multiply-accumulate operation apparatus, the multiply-accumulate operation method including accumulating, by an accumulation register, a value within a preset bit value of a mantissa bitwidth in a result of an addition operation of a shifted first mantissa value and a shifted second mantissa value, determining, by an overflow counter, an overflow count based on an overflow value by which the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bitwidth, performing normalization and rounding based on the value accumulated in the accumulation register and the overflow count, and updating, by an exponent updater, the exponent using a normalized and rounded value.
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公开(公告)号：US20240163445A1
公开(公告)日：2024-05-16
申请号：US18423632
申请日：2024-01-26
Inventor： JUNYAN HUO , YANZHUO MA , WEI ZHANG
IPC: H04N19/132 , G06F5/01 , G06F17/16 , H04N19/159 , H04N19/176 , H04N19/186
CPC classification number: H04N19/132 , G06F5/01 , G06F17/16 , H04N19/159 , H04N19/176 , H04N19/186
Abstract: A method for colour component prediction, an encoder, a decoder and a storage medium are provided. The method includes that: prediction parameters of a current block are determined, the prediction parameters including a prediction mode parameter and a size parameter of the current block; when the prediction mode parameter indicates that a Matrix-based Intra Prediction (MIP) mode is adopted to determine an intra prediction value of the current block, an MIP weight matrix of the current block, a shift factor of the current block and an MIP input sample matrix of the current block are determined; and the intra prediction value of the current block is determined according to the MIP weight matrix, the shift factor and the MIP input sample matrix.
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Patent Agency Ranking
公开(公告)号：US20240152486A1
公开(公告)日：2024-05-09
申请号：US18415958
申请日：2024-01-18
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/544 , G06F9/30 , G06F9/38 , G06F9/48 , G06F9/54 , H03K19/21
CPC classification number: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/5443 , G06F9/30098 , G06F9/3856 , G06F9/4881 , G06F9/54 , H03K19/21 , G06F2207/382
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
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公开(公告)号：US20240134817A1
公开(公告)日：2024-04-25
申请号：US18401571
申请日：2023-12-31
Applicant: Cornami, Inc.
Inventor： Raymond J. Andraka
IPC: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/544 , G06F9/30 , G06F9/38 , G06F9/48 , G06F9/54 , H03K19/21
CPC classification number: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/5443 , G06F9/30098 , G06F9/3856 , G06F9/4881 , G06F9/54 , H03K19/21 , G06F2207/382
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
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8.发明公开公开(公告)号：US20240134599A1
公开(公告)日：2024-04-25
申请号：US18530710
申请日：2023-12-06
Applicant: Visa International Service Association
Inventor： Yan Zheng , Michael Yeh , Junpeng Wang , Wei Zhang , Liang Wang , Hao Yang , Prince Osei Aboagye
Abstract: Provided is a method for normalizing embeddings for cross-embedding alignment. The method may include applying mean centering to the at least one embedding set, applying spectral normalization to the at least one embedding set, and/or applying length normalization to the at least one embedding set. Spectral normalization may include decomposing the at least one embedding set, determining an average singular value of the at least one embedding set, determining a respective substitute singular value for each respective singular value of a diagonal matrix, and/or replacing the at least one embedding set with a product of the at least one embedding set, a right singular vector, and an inverse of the substitute diagonal matrix. The mean centering, spectral normalization, and/or length normalization may be iteratively repeated for a configurable number of iterations. A system and computer program product are also disclosed.
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公开(公告)号：US11941371B2
公开(公告)日：2024-03-26
申请号：US17589345
申请日：2022-01-31
Applicant: Micron Technology, Inc.
Inventor： Vijay S. Ramesh , Katie Blomster Park
Abstract: Systems, apparatuses, and methods related to bit string accumulation are described. A method for bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and modifying a quantity of bits of a result of the iteration of the recursive operation, wherein the modified quantity of bits is less than a threshold quantity of bits. The method can further include writing a first value comprising the modified bits indicative of the result of the iteration of the recursive operation to a first register and writing a second value indicative of the factor corresponding to the result of the iteration of the recursive operation to a second register.
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公开(公告)号：US11907157B2
公开(公告)日：2024-02-20
申请号：US18092247
申请日：2022-12-31
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC: G06F21/44 , G06F15/78 , G06F15/80 , G06F7/523 , G06F7/50 , H03K19/21 , G06F9/48 , G06F9/54 , G06F5/01 , G06F9/30 , G06F7/487 , G06F7/52 , G06F7/544 , G06F9/38
CPC classification number: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/5443 , G06F9/30098 , G06F9/3856 , G06F9/4881 , G06F9/54 , H03K19/21 , G06F2207/382
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
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