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公开(公告)号：US20230153265A1
公开(公告)日：2023-05-18
申请号：US18092247
申请日：2022-12-31
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC: G06F15/80 , G06F9/30 , G06F9/38 , G06F9/54 , G06F7/52 , G06F5/01 , G06F9/48 , G06F7/50 , G06F7/544 , H03K19/21 , G06F7/523 , G06F7/487
CPC classification number: G06F15/80 , G06F9/30098 , G06F9/3855 , G06F9/54 , G06F7/52 , G06F5/01 , G06F9/4881 , G06F7/50 , G06F7/5443 , H03K19/21 , G06F7/523 , G06F7/487 , G06F2207/382
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
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公开(公告)号：US11977509B2
公开(公告)日：2024-05-07
申请号：US17967173
申请日：2022-10-17
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC: G06F7/76 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/544 , G06F9/30 , G06F9/38 , G06F9/48 , G06F9/54 , G06F15/173 , G06F15/80 , H03K19/21
CPC classification number: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/5443 , G06F9/30098 , G06F9/3856 , G06F9/4881 , G06F9/54 , H03K19/21 , G06F2207/382
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
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公开(公告)号：US20220058199A1
公开(公告)日：2022-02-24
申请号：US17467231
申请日：2021-09-05
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Frederick Curtis Furtek , Kim Knuttila , L. Brian McGann
Abstract: Representative embodiments are disclosed for a rapid and highly parallel decompression of compressed executable and other files, such as executable files for operating systems and applications, having compressed blocks including run length encoded (“RLE”) data having data-dependent references. An exemplary embodiment includes a plurality of processors or processor cores to identify a start or end of each compressed block; to partially decompress, in parallel, a selected compressed block into independent data, dependent (RLE) data, and linked dependent (RLE) data; to sequence the independent data, dependent (RLE) data, and linked dependent (RLE) data from a plurality of partial decompressions of a plurality of compressed blocks, to obtain data specified by the dependent (RLE) data and linked dependent (RLE) data, and to insert the obtained data into a corresponding location in an uncompressed file. The representative embodiments are also applicable to other types of data processing for applications having data dependencies.
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公开(公告)号：US11151139B2
公开(公告)日：2021-10-19
申请号：US16900381
申请日：2020-06-12
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Frederick Curtis Furtek , Kim Knuttila , L. Brian McGann
Abstract: Representative embodiments are disclosed for a rapid and highly parallel decompression of compressed executable and other files, such as executable files for operating systems and applications, having compressed blocks including run length encoded (“RLE”) data having data-dependent references. An exemplary embodiment includes a plurality of processors or processor cores to identify a start or end of each compressed block; to partially decompress, in parallel, a selected compressed block into independent data, dependent (RLE) data, and linked dependent (RLE) data; to sequence the independent data, dependent (RLE) data, and linked dependent (RLE) data from a plurality of partial decompressions of a plurality of compressed blocks, to obtain data specified by the dependent (RLE) data and linked dependent (RLE) data, and to insert the obtained data into a corresponding location in an uncompressed file. The representative embodiments are also applicable to other types of data processing for applications having data dependencies.
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公开(公告)号：US20210073171A1
公开(公告)日：2021-03-11
申请号：US17015973
申请日：2020-09-09
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC: G06F15/80 , G06F7/523 , G06F7/50 , G06F9/38 , G06F9/30 , G06F9/48 , G06F9/54 , G06F5/01 , H03K19/21
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
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公开(公告)号：US20180357284A1
公开(公告)日：2018-12-13
申请号：US16108356
申请日：2018-08-22
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Frederick Curtis Furtek , Kim Knuttila , L. Brian McGann
CPC classification number: G06F16/24561 , G06F3/0608 , G06F3/0643 , G06F3/0679 , H03M7/3062 , H03M7/40 , H03M7/4093 , H03M7/42 , H03M7/46 , H03M7/60 , H03M7/6005
Abstract: Representative embodiments are disclosed for a rapid and highly parallel decompression of compressed executable and other files, such as executable files for operating systems and applications, having compressed blocks including run length encoded (“RLE”) data having data-dependent references. An exemplary embodiment includes a plurality of processors or processor cores to identify a start or end of each compressed block; to partially decompress, in parallel, a selected compressed block into independent data, dependent (RLE) data, and linked dependent (RLE) data; to sequence the independent data, dependent (RLE) data, and linked dependent (RLE) data from a plurality of partial decompressions of a plurality of compressed blocks, to obtain data specified by the dependent (RLE) data and linked dependent (RLE) data, and to insert the obtained data into a corresponding location in an uncompressed file. The representative embodiments are also applicable to other types of data processing for applications having data dependencies.
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公开(公告)号：US20170220643A1
公开(公告)日：2017-08-03
申请号：US15493510
申请日：2017-04-21
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Frederick Curtis Furtek , Kim Knuttila , L. Brian McGann
CPC classification number: G06F17/30501 , G06F3/0608 , G06F3/0643 , G06F3/0679 , H03M7/3062 , H03M7/40 , H03M7/4093 , H03M7/42 , H03M7/46 , H03M7/60 , H03M7/6005
Abstract: Representative embodiments are disclosed for a rapid and highly parallel decompression of compressed executable and other files, such as executable files for operating systems and applications, having compressed blocks including run length encoded (“RLE”) data having data-dependent references. An exemplary embodiment includes a plurality of processors or processor cores to identify a start or end of each compressed block; to partially decompress, in parallel, a selected compressed block into independent data, dependent (RLE) data, and linked dependent (RLE) data; to sequence the independent data, dependent (RLE) data, and linked dependent (RLE) data from a plurality of partial decompressions of a plurality of compressed blocks, to obtain data specified by the dependent (RLE) data and linked dependent (RLE) data, and to insert the obtained data into a corresponding location in an uncompressed file. The representative embodiments are also applicable to other types of data processing for applications having data dependencies.
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公开(公告)号：US20240152486A1
公开(公告)日：2024-05-09
申请号：US18415958
申请日：2024-01-18
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/544 , G06F9/30 , G06F9/38 , G06F9/48 , G06F9/54 , H03K19/21
CPC classification number: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/5443 , G06F9/30098 , G06F9/3856 , G06F9/4881 , G06F9/54 , H03K19/21 , G06F2207/382
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
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公开(公告)号：US11907157B2
公开(公告)日：2024-02-20
申请号：US18092247
申请日：2022-12-31
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC: G06F21/44 , G06F15/78 , G06F15/80 , G06F7/523 , G06F7/50 , H03K19/21 , G06F9/48 , G06F9/54 , G06F5/01 , G06F9/30 , G06F7/487 , G06F7/52 , G06F7/544 , G06F9/38
CPC classification number: G06F15/80 , G06F5/01 , G06F7/487 , G06F7/50 , G06F7/52 , G06F7/523 , G06F7/5443 , G06F9/30098 , G06F9/3856 , G06F9/4881 , G06F9/54 , H03K19/21 , G06F2207/382
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
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公开(公告)号：US11494331B2
公开(公告)日：2022-11-08
申请号：US17015973
申请日：2020-09-09
Applicant: Cornami, Inc.
Inventor： Paul L. Master , Steven K. Knapp , Raymond J. Andraka , Alexei Beliaev , Martin A. Franz , Rene Meessen , Frederick Curtis Furtek
IPC: G06F21/44 , G06F15/78 , G06F15/80 , G06F7/523 , G06F7/50 , G06F9/38 , H03K19/21 , G06F9/48 , G06F9/54 , G06F5/01 , G06F9/30 , G06F7/487 , G06F7/52 , G06F7/544
Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.
