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    Folded integer multiplication for field-programmable gate arrays
    1.
    发明授权
    Folded integer multiplication for field-programmable gate arrays 有权

    公开(公告)号：US11960853B2

    公开(公告)日：2024-04-16

    申请号：US17214673

    申请日：2021-03-26

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Bogdan Mihai Pasca

    IPC分类号： G06F7/52 ,  G06F7/523 ,  H03K19/177

    CPC分类号： G06F7/52 ,  G06F7/523 ,  H03K19/177

    摘要： Folded integer multiplier (FIM) circuitry includes a multiplier configurable to perform multiplication and a first addition/subtraction unit and a second addition/subtraction unit both configurable to perform addition and subtraction. The FIM circuitry is configurable to determine each product of a plurality of products for a plurality of pairs of input values having a first number of bits by performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction, and performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits. The plurality of multiplication operations includes a first number of multiplication operations, and the multiplier is configurable to begin performing all multiplication operations of the plurality of multiplication operations within a first number of clock cycles equal to the first number of multiplication operations.

    Computer architecture for performing multiplication using correlithm objects in a correlithm object processing system
    2.
    发明授权
    Computer architecture for performing multiplication using correlithm objects in a correlithm object processing system 有权

    公开(公告)号：US11645096B2

    公开(公告)日：2023-05-09

    申请号：US16521416

    申请日：2019-07-24

    申请人： BANK OF AMERICA CORPORATION

    发明人： Patrick N. Lawrence

    IPC分类号： G06F9/455 ,  G06F7/52 ,  G06F7/50

    CPC分类号： G06F9/45508 ,  G06F7/50 ,  G06F7/52

    摘要： A system includes a memory and a node. The memory stores first and second log string correlithm objects. The node receives first and second real-world numerical values, and identifies a first sub-string correlithm object from the first log string correlithm object that corresponds to the first real-world numerical value. The node aligns the first and second log string correlithm objects such that the first sub-string correlithm object aligns with a sub-string correlithm object from the second log string correlithm object representing the logarithmic value of one. The node identifies a second sub-string correlithm object from the second log string correlithm object that corresponds to the second real-world numerical value, and determines which sub-string correlithm object from the first log string correlithm object aligns with the second sub-string correlithm object from the second log string correlithm object. The node outputs the determined sub-string correlithm object.

    PERFORMING A COMPARISON COMPUTATION IN A COMPUTER SYSTEM
    3.
    发明申请
    PERFORMING A COMPARISON COMPUTATION IN A COMPUTER SYSTEM 审中-公开

    公开(公告)号：US20180143805A1

    公开(公告)日：2018-05-24

    申请号：US15874642

    申请日：2018-01-18

    申请人： Imagination Technologies Limited

    发明人： Leonard Rarick

    IPC分类号： G06F7/52 ,  G06F7/552

    CPC分类号： G06F7/52 ,  G06F7/552 ,  G06F7/5525 ,  G06F2207/5521

    摘要： A method and computer system are provided for performing a comparison computation, e.g. for use in a check procedure for a reciprocal square root operation. The comparison computation compares a multiplication of three values with a predetermined value. The computer system performs the multiplication using multiplier logic which is configured to perform multiply operations in which two values are multiplied together. A first and second of the three values are multiplied to determine a first intermediate result, w1. The digits of w1 are separated into two portions, w1,1 and w1,2. The third of the three values is multiplied with w1,2 and the result is added into a multiplication of the third of the three values with w1,1 to thereby determine the result of multiplying the three values together. In this way the comparison is performed with high accuracy, whilst keeping the area and power consumption of the multiplier logic low.

    METHOD AND APPARATUS FOR COVERAGE ANALYSIS OF SRT LOOK-UP TABLE
    4.
    发明申请
    METHOD AND APPARATUS FOR COVERAGE ANALYSIS OF SRT LOOK-UP TABLE 审中-公开

    公开(公告)号：US20180121341A1

    公开(公告)日：2018-05-03

    申请号：US15341539

    申请日：2016-11-02

    申请人： International Business Machines Corporation

    发明人： Elena Guralnik ,  Haim Kermany

    IPC分类号： G06F11/36 ,  G06F7/52

    CPC分类号： G06F11/3692 ,  G06F7/52 ,  G06F7/535 ,  G06F11/3664 ,  G06F11/3684 ,  G06F11/3688

    摘要： A computer-implemented method, computerized apparatus and computer program product. The method includes receiving at a computing device, a Sweeney-Robertson-Tocher (SRT) implementation, and a look-up table (LUT) used by the SRT implementation; obtaining an assertion for the SRT, the assertion associated with at least one entry from the LUT; verifying the assertion by executing a formal verification engine on the SRT implementation. Subject to the assertion failing, the method further provides a counter example for a computation that when performed by the SRT implementation accesses the at least one entry. Further, subject to the assertion holding, the method performs determining that the at least one entry is unreachable.

    Performing a comparison computation in a computer system
    6.
    发明授权
    Performing a comparison computation in a computer system 有权

    公开(公告)号：US09875083B2

    公开(公告)日：2018-01-23

    申请号：US14452315

    申请日：2014-08-05

    申请人： Imagination Technologies, Limited

    发明人： Leonard Rarick

    IPC分类号： G06F7/52 ,  G06F7/552

    CPC分类号： G06F7/52 ,  G06F7/552 ,  G06F7/5525 ,  G06F2207/5521

    摘要： A method and computer system are provided for performing a comparison computation, e.g. for use in a check procedure for a reciprocal square root operation. The comparison computation compares a multiplication of three values with a predetermined value. The computer system performs the multiplication using multiplier logic which is configured to perform multiply operations in which two values are multiplied together. A first and second of the three values are multiplied to determine a first intermediate result, w1. The digits of w1 are separated into two portions, w1,1 and w1,2. The third of the three values is multiplied with w1,2 and the result is added into a multiplication of the third of the three values with w1,1 to thereby determine the result of multiplying the three values together. In this way the comparison is performed with high accuracy, while keeping the area and power consumption of the multiplier logic low.

    METHOD AND SYSTEM FOR PERFORMING DIVISION/MULTIPLICATION OPERATIONS IN DIGITAL PROCESSORS, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT
    9.
    发明申请
    METHOD AND SYSTEM FOR PERFORMING DIVISION/MULTIPLICATION OPERATIONS IN DIGITAL PROCESSORS, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT 审中-公开
    在数字处理器，对应设备和计算机程序产品中执行部门/多媒体操作的方法和系统

    公开(公告)号：US20140379769A1

    公开(公告)日：2014-12-25

    申请号：US14313273

    申请日：2014-06-24

    申请人： STMicroelectronics S.r.l.

    发明人： Daniele Mangano

    IPC分类号： G06F5/01

    CPC分类号： G06F5/01 ,  G06F7/52 ,  G06F7/523 ,  G06F7/535

    摘要： A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.

    摘要翻译： 数字处理器，例如PID控制器中的分频器，执行数学运算，例如涉及由位信号串和运算符表示的操作数的除法（或乘法）以产生运算结果。 通过将操作者的第一和第二二次近似值识别为操作者的最接近的较低和最接近的较高功率值来配置处理器。 通过使用操作数中的位信号通过使用交替序列中的第一和第二二次近似值来通过操作者的第一和第二二次近似值对输入操作数执行操作 产生：通过使用第二二次近似值的第一近似结果，通过使用第二二次幂近似值的第二近似结果​​。 第一和第二近似结果​​的平均值代表操作的准确结果。

    Phasor-based pulse detection
    10.
    发明授权
    Phasor-based pulse detection 有权
    基于相量的脉冲检测

    公开(公告)号：US08878945B2

    公开(公告)日：2014-11-04

    申请号：US14088304

    申请日：2013-11-22

    申请人： Lockheed Martin Corporation

    发明人： James A. Johnson

    IPC分类号： H04N17/02 ,  H04L27/01 ,  H04B1/10 ,  H04L27/26 ,  G01S7/285 ,  H04B1/16 ,  G06F7/52

    CPC分类号： H04B1/16 ,  G01S7/285 ,  G06F7/52

    摘要： A phasor-based pulse detection system includes a first multiplier stage configured to apply a first delayed conjugate multiplication operation to an input signal. The system can also include a second multiplier stage coupled to the first multiplier stage and configured to apply a second delayed conjugate multiplication operation to an output of the first multiplier stage, and an absolute value unit coupled to the second multiplier stage and configured to perform an absolute value operation on an output of the second multiplier stage. The system can further include video filter stage coupled to the absolute value unit and configured to perform a video filtering operation on an output of the absolute value unit. The system can also include a hysteresis detector coupled to the video filter stage, the hysteresis detector configured for detecting a signal in a filtered video signal received from the video filter stage, the detecting including determining a signal start when the filtered video signal exceeds a predetermined detection threshold for a first predetermined number of consecutive samples, and determining a signal end when the filtered video signal falls below a predetermined rejection threshold for a second predetermined number of consecutive samples.

    摘要翻译： 基于相量的脉冲检测系统包括：第一乘法器级，被配置为对输入信号施加第一延迟共轭乘法运算。 该系统还可以包括耦合到第一乘法器级并被配置为对第一乘法器级的输出施加第二延迟共轭乘法运算的第二乘法器级和耦合到第二乘法器级的绝对值单元，并且被配置为执行 对第二乘法器级的输出进行绝对值运算。 该系统还可以包括耦合到绝对值单元并被配置为对绝对值单元的输出执行视频滤波操作的视频滤波器级。 该系统还可以包括耦合到视频滤波器级的滞后检测器，滞后检测器被配置用于检测从视频滤波器级接收的经过滤波的视频信号中的信号，该检测包括当滤波的视频信号超过预定值时确定信号开始 第一预定数量的连续样本的检测阈值，以及当滤波的视频信号在第二预定数量的连续样本下降到低于预定拒绝阈值时确定信号结束。