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    Fused multiply add pipeline
    1.
    发明授权
    Fused multiply add pipeline 有权
    熔融加倍管道

    公开(公告)号：US09430190B2

    公开(公告)日：2016-08-30

    申请号：US14169864

    申请日：2014-01-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Son Dao Trong ,  Michael Klein ,  Christophe Layer ,  Silvia M. Mueller

    IPC: G06F7/38 ,  G06F7/483 ,  G06F7/53 ,  G06F7/533 ,  G06F7/544

    CPC classification number: G06F7/483 ,  G06F7/5312 ,  G06F7/5338 ,  G06F7/5443

    Abstract: A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor is disclosed. A multiplication is initially performed between a first operand and a second operand in a multiplier block to obtain a set of partial product results. The partial product results are sent to a carry-save adder block. A partial product reduction is performed on the partial product results to generate a carry-save result having a sum term and a carry term. The carry-save result is then formatted to generate a carry-out bit. The carry-save result is added to a third operand to generate a final result.

    Abstract translation: 公开了一种用于在处理器的浮点单元中操作融合加法管线的方法。 最初在乘法器块中的第一操作数和第二操作数之间执行乘法以获得一组部分乘积结果。 部分乘积结果被发送到进位保存加法器块。 对部分产品结果执行部分产品减少以产生具有和项和进位项的进位保存结果。 然后格式化进位保存结果以生成进位位。 进位保存结果被添加到第三个操作数以生成最终结果。

    FORMAL VERIFICATION OF BOOTH MULTIPLIERS
    2.
    发明申请
    FORMAL VERIFICATION OF BOOTH MULTIPLIERS 有权
    引导乘法器的形式验证

    公开(公告)号：US20140067897A1

    公开(公告)日：2014-03-06

    申请号：US14019365

    申请日：2013-09-05

    Applicant: Calypto Design Systems, Inc.

    Inventor： Michael L. Case

    IPC: G06F17/10

    CPC classification number: G06F17/10 ,  G06F7/5338 ,  G06F17/504

    Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be used to formally verify a Booth multiplier. For instance, in one example embodiment, a specification of a Booth multiplier circuit is received; an initial model checking operation is performed for a smaller version of the Booth multiplier circuit; a series of subsequent model checking operations are performed for versions of the Booth multiplier circuit that are incrementally larger than the smaller version of the Booth multiplier circuit, wherein, for each incrementally larger Booth multiplier circuit, two or more model checking operations are performed, the two or more model checking operations representing decomposed proof obligations for showing; and a verification result of the Booth multiplier circuit is output.

    Abstract translation: 下面公开了用于执行正式验证的方法，装置和系统的代表性实施例。 例如，某些实施例可用于正式验证布斯乘数。 例如，在一个示例实施例中，接收布斯乘法电路的规格; 针对较小版本的布斯乘法器电路执行初始模型检查操作; 对展位乘法电路的版本执行一系列后续的模型检查操作，该版本逐渐大于布斯乘数电路的较小版本，其中，对于每个递增较大的布斯乘数电路，执行两个或多个模型检查操作， 两个或多个模型检查操作，表示分解的证明义务; 并输出布斯乘法器电路的验证结果。

    Mechanism for carryless multiplication that employs booth encoding
    3.
    发明授权
    Mechanism for carryless multiplication that employs booth encoding 有权
    采用展位编码的无刷乘法机制

    公开(公告)号：US08667040B2

    公开(公告)日：2014-03-04

    申请号：US12960239

    申请日：2010-12-03

    Applicant: Timothy A. Elliott

    Inventor： Timothy A. Elliott

    IPC: G06F7/00 ,  G06F7/38

    CPC classification number: G06F7/5338

    Abstract: An apparatus having operand registers, an opcode detector, a carryless preformat unit, a compressor, a left shifter, and exclusive-OR logic. The operand registers receive operands for a carryless multiplication. The opcode detector receives a carryless multiplication instruction, and asserts a carryless signal. The carryless preformat unit partitions a first operand into a plurality of parts that are such that a Booth encoder is precluded from selection of second partial products of a second operand, where the second partial products reflect implicit carry operations. The compressor sums first partial products of the second operand via carry save adders arranged in a Wallace tree configuration, where generation of carry bits is disabled. The left shifter shifts one or more outputs of the compressor. The exclusive-OR logic executes an exclusive-OR function to yield a carryless multiplication result.

    Abstract translation: 具有操作数寄存器的装置，操作码检测器，无卡式预格式化单元，压缩器，左移位器和异或逻辑。 操作数寄存器接收无刷乘法的操作数。 操作码检测器接收无轮乘法指令，并且断言无卡信号。 无卡块预格式单元将第一操作数分割成多个部分，使得布斯编码器不被选择第二部分乘积的第二操作数的选择，其中第二部分乘积反映隐式进位操作。 压缩器通过在Wallace树配置中布置的进位保存加法器对第二操作数的第一部分乘积求和，其中进位位的生成被禁用。 左移位器移动压缩机的一个或多个输出。 异或逻辑执行异或运算以产生无轮乘积结果。

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