公开(公告)号：US12099850B2

公开(公告)日：2024-09-24

申请号：US17959507

申请日：2022-10-04

申请人： Dell Products L.P.

发明人： Elie Antoun Jreij ,  Austin Patrick Bolen

IPC分类号： G06F9/44 ,  G06F9/38 ,  G06F9/4401

CPC分类号： G06F9/4406 ,  G06F9/3824 ,  G06F9/4411

摘要： A node, that includes a processor executing a first operating system, a peripheral port connected to a peripheral device, where the peripheral port is configured to block access to the peripheral device, a system control processor executing a second operating system, where the system control processor is configured to perform a method for providing access of the peripheral device to the first operating system, the method that includes receiving a peripheral access message from a remote authentication server, where the peripheral access message includes a peripheral device identifier associated with the peripheral device, and in response to receiving the peripheral access message, unblocking the access to the peripheral device.

公开(公告)号：US11966739B2

公开(公告)日：2024-04-23

申请号：US17941387

申请日：2022-09-09

申请人： Arm Limited

发明人： Matthew James Walker ,  Mbou Eyole ,  Giacomo Gabrielli ,  Balaji Venu

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC分类号： G06F9/30123 ,  G06F9/30138 ,  G06F9/3824 ,  G06F9/4881 ,  G06F9/30098 ,  G06F9/30145

摘要： There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.

公开(公告)号：US11941402B2

公开(公告)日：2024-03-26

申请号：US17737922

申请日：2022-05-05

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/345 ,  G06F9/355 ,  G06F15/80

CPC分类号： G06F9/3824 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/355 ,  G06F15/8053

摘要： Disclosed herein are vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors. It is known to use scalar index registers in vector processors to access multiple positions of vectors by changing the scalar index registers in vector operations. By using a vector indexing register for indexing positions of one or more operand vectors, the scalar index register can be replaced and at least the continual changing of the scalar index register can be avoided.

公开(公告)号：US20230385059A1

公开(公告)日：2023-11-30

申请号：US18449651

申请日：2023-08-14

申请人： Intel Corporation

发明人： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3001 ,  G06F9/30145 ,  G06F9/3005 ,  G06F9/30036 ,  G06F9/383 ,  G06F9/3016 ,  G06F9/30109 ,  G06F9/30123 ,  G06F9/30076 ,  G06F9/3824 ,  G06F9/30043

摘要： Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

公开(公告)号：US11726912B2

公开(公告)日：2023-08-15

申请号：US17216563

申请日：2021-03-29

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas C. Burger ,  Aaron L. Smith ,  Gagan Gupta ,  David T. Harper

IPC分类号： G06F9/30 ,  G06F12/0804 ,  G06F9/38 ,  G06F12/0844

CPC分类号： G06F12/0804 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/383 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0844 ,  G06F2212/1032

摘要： Systems and methods are disclosed for performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.

公开(公告)号：US11656992B2

公开(公告)日：2023-05-23

申请号：US16548116

申请日：2019-08-22

申请人： Western Digital Technologies, Inc.

发明人： Marjan Radi ,  Dejan Vucinic

IPC分类号： G06F12/00 ,  G06F12/0862 ,  G06F12/0806 ,  G06F12/0802 ,  H04L67/1097 ,  G06F12/0817 ,  H04L67/568 ,  G06F9/38 ,  G06F9/34

CPC分类号： G06F12/0862 ,  G06F12/0802 ,  G06F12/082 ,  G06F12/0806 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0828 ,  H04L67/1097 ,  H04L67/568 ,  G06F9/34 ,  G06F9/3824 ,  G06F2212/154 ,  G06F2212/602

摘要： A programmable switch receives a cache line request from a client of a plurality of clients on a network to obtain a cache line. One or more additional cache lines are identified based on the received cache line request and prefetch information. The cache line and the one or more additional cache lines are requested from one or more memory devices on the network. The requested cache line and the one or more additional cache lines are received from the one or more memory devices, and are sent to the client.

公开(公告)号：US20190250921A1

公开(公告)日：2019-08-15

申请号：US16398183

申请日：2019-04-29

申请人： Intel Corporation

发明人： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/1027 ,  G06F12/0875 ,  G06F13/42 ,  G06F15/80

CPC分类号： G06F9/3853 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/30163 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

摘要： According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20190012175A1

公开(公告)日：2019-01-10

申请号：US16117058

申请日：2018-08-30

申请人： International Business Machines Corporation

发明人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30087 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861

摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

公开(公告)号：US20180217841A1

公开(公告)日：2018-08-02

申请号：US15849333

申请日：2017-12-20

申请人： Intel Corporation

发明人： TAL ULIEL ,  ROBERT VALENTINE

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3867

摘要： A method is described that includes fetching an instruction. The method further includes decoding the instruction. The instruction specifies an operation, a first operand and a second operand. The method further includes fetching the first and second operands of the instruction. The first and second operands are each composed of a plurality of larger chunks having constituent elements. The method further includes performing the operation specified by the instruction including generating a resultant composed of a plurality of larger chunks having constituent elements. The generating of the resultant includes selecting for each element in the resultant a contiguous group of bits from a same positioned chunk of the first operand as the chunk of the element in the resultant, the contiguous group of bits being identified by a same positioned element of the second operand as the element in the resultant.

公开(公告)号：US10037211B2

公开(公告)日：2018-07-31

申请号：US15077015

申请日：2016-03-22

申请人： International Business Machines Corporation

发明人： Kimberly M. Fernsler ,  David A. Hrusecky ,  Hung Q. Le ,  Elizabeth A. McGlone ,  Brian W. Thompto

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/00 ,  G06F13/38 ,  G06F12/0875 ,  G06F9/30 ,  G06F13/40

CPC分类号： G06F9/3851 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3855 ,  G06F12/0875 ,  G06F13/4068 ,  G06F2212/452

摘要： Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where each load/store slice includes a load miss queue and a load reorder queue, includes: receiving, at a load reorder queue, a load instruction requesting data; responsive to the data not being stored in a data cache, determining whether a previous load instruction is pending a fetch of a cache line comprising the data; if the cache line does not comprise the data, allocating an entry for the load instruction in the load miss queue; and if the cache line does comprise the data: merging, in the load reorder queue, the load instruction with an entry for the previous load instruction.