公开(公告)号：US11954490B2

公开(公告)日：2024-04-09

申请号：US18309469

申请日：2023-04-28

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Robert Valentine ,  Bret Toll ,  Christopher J. Hughes ,  Alexander F. Heinecke ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

IPC: G06F17/16 ,  G06F7/53 ,  G06F9/30

CPC classification number: G06F9/30167 ,  G06F9/30101 ,  G06F9/30149

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transform matrices into a row-interleaved format. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of source and destination matrices, wherein the opcode indicates that the processor is to transform the specified source matrix into the specified destination matrix having the row-interleaved format; and execution circuitry to respond to the decoded instruction by transforming the specified source matrix into the specified RowInt-formatted destination matrix by interleaving J elements of each J-element sub-column of the specified source matrix in either row-major or column-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements.

公开(公告)号：US11614936B2

公开(公告)日：2023-03-28

申请号：US17216566

申请日：2021-03-29

Applicant: Intel Corporation

Inventor： Alexander F. Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Raanan Sade ,  Menachem Adelman ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.

公开(公告)号：US11327894B2

公开(公告)日：2022-05-10

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20220129264A1

公开(公告)日：2022-04-28

申请号：US17517351

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark Charney ,  Raanan Sade ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Roman S. Dubtsov

IPC: G06F9/30 ,  G06F7/48

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

公开(公告)号：US11249761B2

公开(公告)日：2022-02-15

申请号：US16934003

申请日：2020-07-20

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US11093247B2

公开(公告)日：2021-08-17

申请号：US15858932

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F15/00 ,  G06F9/30

Abstract: Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded load matrix pair instruction to load every element of left and right tiles of the identified destination matrix from corresponding element positions of left and right tiles of the identified source matrix, respectively, wherein the executing operates on one row of the identified destination matrix at a time, starting with the first row.

公开(公告)号：US11068262B2

公开(公告)日：2021-07-20

申请号：US17133078

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Alexander F. Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Raanan Sade ,  Menachem Adelman ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to systems and methods for performing instructions to convert to 16-bit floating-point format. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising N single-precision elements, and a destination vector comprising at least N 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to 16-bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.

公开(公告)号：US20210141683A1

公开(公告)日：2021-05-13

申请号：US17020663

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US10324857B2

公开(公告)日：2019-06-18

申请号：US15416549

申请日：2017-01-26

Applicant: Intel Corporation

Inventor： Joseph Nuzman ,  Raanan Sade ,  Igor Yanover ,  Ron Gabor ,  Amit Gradstein

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1027

Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.

公开(公告)号：US20190163473A1

公开(公告)日：2019-05-30

申请号：US15824333

申请日：2017-11-28

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark Charney ,  Raanan Sade ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Roman S. Dubtsov

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F7/4806 ,  G06F7/4812 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3824 ,  G06F17/10

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.