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    Shared virtual address spaces
    2.
    发明授权
    Shared virtual address spaces 有权

    公开(公告)号：US12277065B2

    公开(公告)日：2025-04-15

    申请号：US17647580

    申请日：2022-01-10

    Applicant: Micron Technology, Inc.

    Inventor： Bryan Hornung ,  Tony M. Brewer

    IPC: G06F12/10

    Abstract: Methods, systems, and devices for shared virtual address spaces are described. In some examples, a globally shared address space may be shared across a plurality of memory devices that are included in one or more domains. A host system may set parameters for determining whether an address (e.g., a virtual address) is included within the globally shared address space, and whether the address is associated with a memory device. When a memory device receives a memory request (e.g., a data packet), a processing unit of the memory device may determine whether an address included in the memory request is associated with the memory device. The processing unit may either initiate an access operation on a physical address of the memory device or transmit the memory request to another memory device.

    Techniques for managing writes in nonvolatile memory
    3.
    发明授权
    Techniques for managing writes in nonvolatile memory 有权

    公开(公告)号：US12271633B2

    公开(公告)日：2025-04-08

    申请号：US18625096

    申请日：2024-04-02

    Applicant: Radian Memory Systems, LLC

    Inventor： Mike Jadon ,  Andrey V. Kuzmin ,  Robert Lercari

    IPC: G06F3/06 ,  G06F12/10

    Abstract: This disclosure provides techniques for managing writes of data useful for storage systems that do not permit overwrite of a logical address. One implementation provides a nonvolatile memory storage drive, such as a flash memory drive, that provides support for zoned drive and/or Open Channel-compliant architectures. Circuitry on the storage drive tracks storage location release metadata for addressable memory space, optionally providing to a host system information upon which maintenance decisions or related scheduling can be based. The storage drive can also provide buffering support for accommodating receipt of out-of-order writes and unentanglement and performance of out of order writes, with buffering resources being configurable according to any one of a number of parameters. The disclosed storage drive facilitates reduced error rates and lower request traffic in a manner consistent with newer memory standards that mandate that writes to logical addresses be sequential.

    Efficient logical to physical mapping updates
    5.
    发明授权
    Efficient logical to physical mapping updates 有权

    公开(公告)号：US12242386B2

    公开(公告)日：2025-03-04

    申请号：US18316664

    申请日：2023-05-12

    Applicant: Western Digital Technologies, Inc.

    Inventor： Dinesh Kumar Agarwal ,  Leeladhar Agarwal ,  Lawrence Vazhapully Jacob

    IPC: G06F12/10 ,  G06F12/0804 ,  G06F12/1009

    Abstract: Various devices, such as storage devices or systems are configured to efficiently process and update logical mappings within control table sets. Control table sets are often groupings of logical mapping corresponding to the logical locations of data requested by a host-computing device and the physical locations of the data within the memory array. As data is written and erased, these mappings must be updated within the control table set. Received changes to these mappings are typically stored and updated in two locations: a cache memory and a control table update list. By tracking and marking various control table sets as dirty or having undergone multiple changes, additional received updates can be stored and updated in only the cache memory, bypassing the second control table change list. By only utilizing one method of updating control table sets, processing overhead is reduced and various read or write activities are more efficiently done.

    Failure analysis system of semiconductor device, failure analysis method of semiconductor device, and non-transitory computer readable medium
    6.
    发明授权
    Failure analysis system of semiconductor device, failure analysis method of semiconductor device, and non-transitory computer readable medium 有权

    公开(公告)号：US12235770B2

    公开(公告)日：2025-02-25

    申请号：US17180919

    申请日：2021-02-22

    Applicant: Kioxia Corporation

    Inventor： Mami Kodama ,  Yoshikazu Iizuka ,  Masahiro Noguchi ,  Yumiko Watanabe

    IPC: G06F12/10 ,  G05B23/02

    Abstract: According to one embodiment, the failure analysis system of the semiconductor device includes a memory, a failure information management table, and an analyzing unit. The memory stores normal/failure information collected in a block unit and a column unit in a chip, in a plurality of inspection processes of the semiconductor memory. The failure information management table stores the normal/failure information in the block unit and the column unit stored in the memory, with an addition of product information, fabricating information including a lot number, a wafer number, and a chip address, process information, and test information, which are common information ranging over the inspection processes. The analyzing unit analyzes the normal/failure information in the block unit and the column unit ranging over the plurality of inspection processes, on the basis of the information stored in the failure information management table.

    Techniques for managing writes in nonvolatile memory
    7.
    发明申请
    Techniques for managing writes in nonvolatile memory 有权

    公开(公告)号：US20250053338A1

    公开(公告)日：2025-02-13

    申请号：US18625096

    申请日：2024-04-02

    Applicant: Radian Memory Systems, LLC

    Inventor： Mike Jadon ,  Andrey V. Kuzmin ,  Robert Lercari

    IPC: G06F3/06 ,  G06F12/10

    Abstract: This disclosure provides techniques for managing writes of data useful for storage systems that do not permit overwrite of a logical address. One implementation provides a nonvolatile memory storage drive, such as a flash memory drive, that provides support for zoned drive and/or Open Channel-compliant architectures. Circuitry on the storage drive tracks storage location release metadata for addressable memory space, optionally providing to a host system information upon which maintenance decisions or related scheduling can be based. The storage drive can also provide buffering support for accommodating receipt of out-of-order writes and unentanglement and performance of out of order writes, with buffering resources being configurable according to any one of a number of parameters. The disclosed storage drive facilitates reduced error rates and lower request traffic in a manner consistent with newer memory standards that mandate that writes to logical addresses be sequential.

    Application-transparent near-memory processing architecture with memory channel network
    9.
    发明授权
    Application-transparent near-memory processing architecture with memory channel network 有权

    公开(公告)号：US12210473B2

    公开(公告)日：2025-01-28

    申请号：US17980685

    申请日：2022-11-04

    Applicant: The Board of Trustees of the University of Illinois

    Inventor： Nam Sung Kim ,  Mohammad Alian

    IPC: G06F13/40 ,  G06F12/10 ,  G06F13/16

    Abstract: A computing device includes a host processor to execute a host driver to create a host-side interface, the host-side interface emulating a first Ethernet interface, assign the host-side interface a first medium access control (MAC) address and a first Internet Protocol (IP) address. Memory components are disposed on a substrate. A memory channel network (MCN) processor is disposed on the substrate and coupled between the memory components and the host processor. The MCN processor is to execute an MCN driver to create a MCN-side interface, the MCN-side interface emulating a second Ethernet interface. The MCN processor is to assign the MCN-side interface a second MAC address and a second IP address, which identify the MCN processor as a MCN network node to the host processor.

    Non-stalling, non-blocking translation lookaside buffer invalidation
    10.
    发明授权
    Non-stalling, non-blocking translation lookaside buffer invalidation 有权

    公开(公告)号：US12210459B2

    公开(公告)日：2025-01-28

    申请号：US18303183

    申请日：2023-04-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daniel Brad Wu

    IPC: G06F12/10 ,  G06F9/46 ,  G06F9/48 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1027 ,  H03M13/15

    Abstract: A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

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