公开(公告)号：US12132832B2

公开(公告)日：2024-10-29

申请号：US17136775

申请日：2020-12-29

申请人： Micron Technology, Inc.

发明人： Giuseppe Cariello ,  Gaspare Giglio ,  Patrick Miesen ,  Jonathan Scott Parry

IPC分类号： H04L9/08 ,  G06F12/14

CPC分类号： H04L9/0891 ,  G06F12/14 ,  G06F2212/1052

摘要： Secure methods are described for modifying, erasing, or updating security keys for protected regions of a memory device by using a special firmware object (a key-modification firmware) loaded to the memory device that contains instructions to reprogram, modify, and/or erase the keys. To ensure that this key-modification firmware does not become a security risk, the key-modification firmware object may be protected from subsequent usage in a variety of ways.

公开(公告)号：US20240357804A1

公开(公告)日：2024-10-24

申请号：US18757580

申请日：2024-06-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC分类号： H10B20/20 ,  G06F12/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00

CPC分类号： H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

摘要： A memory device includes: a substrate; a semiconductor fin over the substrate in a first direction; a first gate electrode and a second gate electrode over the substrate in a second direction, the semiconductor fin extending through the second gate electrode and terminating at the first gate electrode; a first gate dielectric layer arranged between the semiconductor fin and the first gate electrode; and a second gate dielectric layer arranged between the semiconductor fin and the second gate electrode. The second gate electrode is configured as a read transistor of a first memory cell, in which the second gate dielectric layer is kept intact, and the first gate electrode is configured as a program transistor of the first memory cell, in which an occurrence or an absence of an electrical breakdown in the first gate dielectric layer represents a binary logic state of the first memory cell.

公开(公告)号：US20240354262A1

公开(公告)日：2024-10-24

申请号：US18760305

申请日：2024-07-01

申请人： Microsoft Technology Licensing, LLC

发明人： Stefan SAROIU ,  Alastair WOLMAN ,  Lucian COJOCAR ,  Kevin Robert LOUGHLIN

IPC分类号： G06F12/14 ,  G06F12/0893 ,  G06F12/1009 ,  G06F21/55

CPC分类号： G06F12/1425 ,  G06F12/0893 ,  G06F12/1009 ,  G06F21/556 ,  G06F2212/1052

摘要： Aspects of the present disclosure relate to techniques for minimizing the effects of RowHammer and induced charge leakage. In examples, systems and methods for preventing access pattern attacks in random-access memory (RAM) are provided. In aspects, a data request associated with a page table may be determined to be a potential security risk and such potential security risk may be mitigated by randomly selecting a memory region from a subset of memory regions, copying data stored in a memory region associated with a page table entry in the page table to the second memory region, disassociating the second memory region from the subset of memory regions and associating the memory region associated with the page table to the second memory region, and updating the page table entry in the page table to refer to the second memory region.

公开(公告)号：US12124347B2

公开(公告)日：2024-10-22

申请号：US18152797

申请日：2023-01-11

申请人： NXP B.V.

发明人： Neha Srivastava ,  Gautam Tikoo ,  Harshit Saxena

IPC分类号： G06F11/27 ,  G06F12/14

CPC分类号： G06F11/27 ,  G06F12/14 ,  G06F2212/1052

摘要： An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.

公开(公告)号：US20240345966A1

公开(公告)日：2024-10-17

申请号：US18293858

申请日：2022-03-04

申请人： Sony Group Corporation

发明人： Yuuichi Nakamura

IPC分类号： G06F12/14 ,  G06F12/0871

CPC分类号： G06F12/1466 ,  G06F12/0871 ,  G06F2212/1052

摘要： An information processing device (100) includes a plurality of CPUs (1), a plurality of cache memories (2) associated with the plurality of CPUs (1), and a main memory (3), each of the plurality of CPUs (1) acquires a lock for exclusively accessing data in the main memory (3), and then accesses the data, data related to access of a corresponding CPU (1) and a lock ID for specifying the lock related to the access are associated and written in a cache 10 line of each of the plurality of cache memories (2), and a cache line of each of the plurality of cache memories (2) is flushed when a CPU (1) other than the corresponding CPU (1) acquires the lock specified based on the lock ID written in the cache line.

公开(公告)号：US12118076B2

公开(公告)日：2024-10-15

申请号：US18130093

申请日：2023-04-03

申请人： Ventana Micro Systems Inc.

发明人： John G. Favor ,  Srivatsan Srinivasan

IPC分类号： G06F12/00 ,  G06F9/455 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0895 ,  G06F12/1045 ,  G06F12/14 ,  G06F21/52 ,  G06F21/55

CPC分类号： G06F21/52 ,  G06F9/45558 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0895 ,  G06F12/1054 ,  G06F12/1408 ,  G06F12/1458 ,  G06F21/556 ,  G06F2009/45583 ,  G06F2009/45587

摘要： A physically-tagged data cache memory mitigates side channel attacks by using a translation context (TC). With each entry allocation, control logic uses the received TC to perform the allocation, and with each access uses the received TC in a hit determination. The TC includes an address space identifier (ASID), virtual machine identifier (VMID), a privilege mode (PM) or translation regime (TR), or combination thereof. The TC is included in a tag of the allocated entry. Alternatively, or additionally, the TC is included in the set index to select a set of entries of the cache memory. Also, the TC may be hashed with address index bits to generate a small tag also included in the allocated entry used to generate an access early miss indication and way select.

公开(公告)号：US12105644B2

公开(公告)日：2024-10-01

申请号：US18198782

申请日：2023-05-17

申请人： Lodestar Licensing Group LLC

发明人： Nathaniel J. Meier ,  Brenton P. Van Leeuwen

IPC分类号： G06F12/14 ,  G06F3/06 ,  G06F21/62 ,  G06F21/79 ,  G11C11/4074 ,  G11C17/16 ,  H04L9/32

CPC分类号： G06F12/1433 ,  G06F12/1466 ,  G06F21/79 ,  G11C11/4074 ,  G11C17/16 ,  G06F3/0622 ,  G06F3/0637 ,  G06F12/14 ,  G06F12/1458 ,  G06F2212/1052

摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

公开(公告)号：US12105642B2

公开(公告)日：2024-10-01

申请号：US17804409

申请日：2022-05-27

申请人： Idemia Identity & Security France

发明人： Hervé Chabanne ,  Linda Guiga ,  Sébastien Bahloul

IPC分类号： G06F12/14 ,  H04L9/32

CPC分类号： G06F12/1408 ,  H04L9/3239 ,  G06F2212/1052

摘要： The invention relates to a method for enrolling data in order to verify the authenticity of a security datum, the method comprising implementing by data processing means of a server the steps of: obtaining a reference security datum, generating a first encoded datum by applying to the reference security datum an obfuscated fuzzy Hamming distance encoding procedure, determining from the reference security datum, a plurality of derived data of the reference security datum, generating a first random datum, and determining a second encoded datum such that a variable point comparison predicate parameterized by the second encoded datum and the first random datum is true when said variable point has as coordinates said derived data, storing on a data storage means of the server at least said first and second encoded data. The invention also relates to a verification method and a server for this purpose.

公开(公告)号：US12105629B2

公开(公告)日：2024-10-01

申请号：US17890604

申请日：2022-08-18

申请人： Samsung Electronics Co., Ltd.

发明人： Zongwang Li ,  Sahand Salamat ,  Rekha Pitchumani

IPC分类号： G06F12/0817 ,  G06F12/14

CPC分类号： G06F12/0828 ,  G06F12/1458

摘要： Provided is a method of data storage, the method including receiving, from an application, a request to access data stored on a storage device, identifying a data access pattern of the application, and storing the data in a cache of the storage device based on the data access pattern.

公开(公告)号：US12099866B2

公开(公告)日：2024-09-24

申请号：US17135381

申请日：2020-12-28

申请人： Advanced Micro Devices, Inc.

发明人： Jonathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

IPC分类号： G06F9/48 ,  G06F3/06 ,  G06F12/02 ,  G06F12/14

CPC分类号： G06F9/485 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/145

摘要： An Address Mapping-Aware Tasking (AMAT) mechanism manages compute task data and issues compute tasks on behalf of threads that created the compute task data. The AMAT mechanism stores compute task data generated by host threads in a set of partitions, where each partition is designated for a particular memory module. The AMAT mechanism maintains address mapping data that maps address information to partitions. Threads push compute task data to the AMAT mechanism instead of generating and issuing their own compute tasks. The AMAT mechanism uses address information included in the compute task data and the address mapping data to determine partitions in which to store the compute task data. The AMAT mechanism then issues compute tasks to be executed near the corresponding memory modules (i.e., in PIM execution units or NUMA compute nodes) based upon the compute task data stored in the partitions.