公开(公告)号：US20250072107A1

公开(公告)日：2025-02-27

申请号：US18944448

申请日：2024-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGIL PARK ,  JAE HYUN PARK ,  DAEWON HA ,  KYUMAN HWANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

公开(公告)号：US20250072059A1

公开(公告)日：2025-02-27

申请号：US18455500

申请日：2023-08-24

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Abhijeet PAUL ,  Hyunchul JUNG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A radio frequency (RF) device is described. The RF device includes a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region. The RF device also includes a transistor including a source region and a drain region in the first-type diffusion region, a gate region between the source region and the drain region, and a body region. The RF device further includes a second-type diffusion region, comprising a gate overlap region partially overlapped by the gate region to define the body region and a second-type diffusion encroachment region in the source region and adjoining the gate overlap region to form a body terminal region, in which a silicidation layer shorts the body terminal region to the source region.

公开(公告)号：US20250072047A1

公开(公告)日：2025-02-27

申请号：US18801861

申请日：2024-08-13

Applicant: Hangzhou Silicon-Magic Semiconductor Technology Co.,Ltd

Inventor： Yanggang OU ,  Jiakun WANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a current spreading layer, a gate trench, a gate electrode, a first body region, a first source region, a second body region and a second source region. The first body region is beneath and in contact with the gate trench. The first source region is formed in the first body region. The second body region extends from a first surface of the current spreading layer into the current spreading layer and adjoins a first sidewall of the gate trench. The second source region is formed in the second body region and adjoins the first sidewall of the gate trench.

公开(公告)号：US20250072038A1

公开(公告)日：2025-02-27

申请号：US18237811

申请日：2023-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi Hong Wang ,  Hui-Hsuan Kung ,  Yi-Lii Huang ,  Chih-Hsiao Chen

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

Abstract: Embodiments of the present disclosure provide a FinFET semiconductor including a first set of fin structures that are active, a source/drain (S/D) region in contact with the first set of fin structures, a second set of fin structures separated, via a shallow trench isolation (STI) feature, from the first set of fin structures, a contact etch stop layer (CESL) over the S/D region and over the second set of fin structures, and a gate over the first set of fin structures and over the second set of fin structures, the gate including a gate dielectric and a gate electrode over the gate dielectric. The second set of fin structures includes one or more non-active fin structures that are in contact with the CESL without being in contact with the S/D region.

公开(公告)号：US20250072035A1

公开(公告)日：2025-02-27

申请号：US18369209

申请日：2023-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Cheng-Yu Ho

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a first oxide layer and a gate structure. The first oxide layer is disposed on a substrate. The gate structure is disposed on the first oxide layer. The gate structure includes a gate and a spacer surrounding the gate. The first oxide layer includes an exposed segment not covered by the gate structure. A thickness of the first oxide layer right below the gate is fixed, and the thickness of the first oxide layer right below the gate is greater than a thickness of the exposed segment.

公开(公告)号：US20250072021A1

公开(公告)日：2025-02-27

申请号：US18237034

申请日：2023-08-23

Applicant: Unity Power Technology Limited

Inventor： Wai Tien CHAN

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

Abstract: A silicon carbide MOSFET device which contains a N-Channel MOSFET, and a JFET connected to the N-Channel MOSFET such that their drain-source current paths are connected in series. A gate of the JFET is connected to a gate of the N-Channel MOSFET device via a voltage divider, which is formed monolithically with the silicon carbide substrate and the first to fourth silicon carbide layers. The protection gate structure can shield the trench oxide from high drain voltage during off-state. The voltage divider is configured to restrict a gate voltage of the JFET such that a SiC PN diode formed within the silicon carbide MOSFET device is turned off when the N-Channel MOSFET is on or off.

公开(公告)号：US12237419B2

公开(公告)日：2025-02-25

申请号：US17668143

申请日：2022-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

公开(公告)号：US12237413B2

公开(公告)日：2025-02-25

申请号：US18447783

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

Inventor： Lianjie Li ,  Feng Han ,  Jian-Hua Lu ,  Yanbin Lu ,  Shui Liang Chen

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

Abstract: An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

公开(公告)号：US12237410B1

公开(公告)日：2025-02-25

申请号：US18937369

申请日：2024-11-05

Applicant: JSAB TECHNOLOGIES (SHENZHEN) LTD.

Inventor： Yong Liu ,  Hao Feng ,  Xin Peng ,  Johnny Kin On Sin

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: A trench gate silicon carbide metal oxide semiconductor field effect transistor (MOSFET) device and a fabrication method thereof. A second conductive heavily doped layer at the bottom corner of a trench gate is electrically connected to a second conductive heavily doped layer on another side edge of the trench gate through a layout design, which ensures a ground potential during voltage blocking state. This design protects the insulating layer in the trench gate and the Schottky contact in a junction barrier Schottky (JBS) diode, thereby enhancing device reliability. Moreover, in a diode operating mode, P+ on the left and right sides of the trench gate are connected to a positive potential. When the P+/N− junction is activated, the conductivity modulation can be implemented through hole injection, thereby improving the device's ability to withstand surge current impacts.

公开(公告)号：US12237376B2

公开(公告)日：2025-02-25

申请号：US17565254

申请日：2021-12-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Jiun-Yun Li ,  Pao-chuan Shih ,  Wei-Chih Hou

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/73 ,  H01L29/78

Abstract: The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.