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1.发明公开公开(公告)号：US20240355925A1
公开(公告)日：2024-10-24
申请号：US18390943
申请日：2023-12-20
Inventor： Yanggang Ou , Jiamin Luo
IPC: H01L29/78 , H01L29/423 , H01L29/66
CPC classification number: H01L29/7835 , H01L29/4236 , H01L29/6659
Abstract: A gate-source structure of an asymmetric trench MOSFET, includes: a substrate of a first doping type; an epitaxial layer of the first doping type on the substrate; a current spreading layer of the first doping type in the epitaxial layer; a trench extending from a surface to an inside of the current spreading layer; a source conductor located in the trench; a first dielectric layer, located between the source conductor and an inner surface of the trench, isolating from the source conductor and the inner surface of the trench; a gate conductor located in the trench; an isolation dielectric layer, located between the source conductor and the gate conductor, isolating from the source conductor and the gate conductor; and a gate dielectric layer, located between the gate conductor and the inner surface of the trench, isolating from the gate conductor and the inner surface of the trench.
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公开(公告)号：US11894440B2
公开(公告)日：2024-02-06
申请号：US17479314
申请日：2021-09-20
Inventor： Jiakun Wang , Hui Chen
CPC classification number: H01L29/66068 , H01L21/047 , H01L21/0465 , H01L29/7827 , H01L29/1095
Abstract: Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.
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公开(公告)号：US20230207685A1
公开(公告)日：2023-06-29
申请号：US18089726
申请日：2022-12-28
Inventor： Jinyong Cai , Shida Dong , Jiakun Wang
IPC: H01L29/78 , H01L29/423 , H01L29/40 , H01L29/66
CPC classification number: H01L29/7813 , H01L29/42376 , H01L29/407 , H01L29/401 , H01L29/66734
Abstract: Disclosed is a split-gate MOSFET and a manufacturing method, including: forming a first trench in a semiconductor layer; forming a second trench communicated with the first trench by using the first trench; forming a first dielectric layer in the second trench, a second dielectric layer in the first trench; forming a first conductor, located in the second trench, isolated from the semiconductor layer by the first dielectric layer; forming a third dielectric layer covering the first conductor; forming a second conductor, located in the first trench, isolated from the semiconductor layer by the second dielectric layer, the first conductor being isolated from the second conductor by the third dielectric layer; forming a body region adjacent to the first trench, the first trench has an inner diameter greater than that of the second trench. Thus, process window is expanded and beneficial to forming the third dielectric layer.
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公开(公告)号：US20230117590A1
公开(公告)日：2023-04-20
申请号：US17931034
申请日：2022-09-09
IPC: H01L29/10 , H01L29/16 , H01L29/08 , H01L29/417 , H01L29/78
Abstract: A silicon carbide power semiconductor device is provided, including a substrate, a drift region, a body region, a source region, a base region, a shielding region, a JFET region, a gate structure, an insulating layer, and a source metal layer. The source contacting window has first edges within second edges of the body region corresponding to the first edges, and the source metal layer abuts only a part of the source region. The area of the silicon carbide power semiconductor device of the present disclosure is thus reduced. Therefore, the ratio of the channel length to the area of the silicon carbide power semiconductor device and the ratio of the area of the JFET region to the area of the silicon carbide power semiconductor device are increased, whereby the specific on-resistance of the silicon carbide power semiconductor device is reduced.
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公开(公告)号：US20230077336A1
公开(公告)日：2023-03-16
申请号：US17944284
申请日：2022-09-14
Inventor： Jian Liu , Jinyong Cai
IPC: H01L29/417 , H01L29/40 , H01L29/78 , H01L29/66
Abstract: Disclosed is a method for manufacturing a conducting path in a doped region, comprising: forming a dielectric layer on a semiconductor layer which includes the doped region; forming an opening in the dielectric layer; forming a side wall on sidewall of the opening; etching the semiconductor layer through the opening to form a conduction hole extending to the doped region; filling the conduction hole with conductive material to form a conducting path, wherein the side wall reduces a transverse dimension of the conducting path. According to the method for manufacturing the conducting path in the doped region in the present disclosure, by forming the side wall on sidewall of the opening in the dielectric layer, the transverse dimension of the opening in the dielectric layer is reduced, thereby the semiconductor layer is etched with a narrower opening to obtain the conduction hole with a smaller size, device performance is improved.
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Patent Agency Ranking
公开(公告)号：US11424344B2
公开(公告)日：2022-08-23
申请号：US17091225
申请日：2020-11-06
Inventor： Jiakun Wang , Bing Wu
IPC: H01L29/423 , H01L29/66 , H01L21/308 , H01L29/78
Abstract: A method of manufacturing a trench MOSFET can include: forming a trench extending from an upper surface of a semiconductor base layer to internal portion of the semiconductor base layer; forming a first insulating layer covering sidewall and bottom surfaces of the trench and the upper surface of the semiconductor base layer; forming a shield conductor filling a lower portion of the trench, where the first insulating layer separates the shield conductor from the semiconductor base layer; forming a second insulating layer covering a top surface of the shield conductor, where the first insulating layer separates the second insulating layer from the semiconductor base layer, and the first and second insulating layers conformally form a dielectric layer; and removing the dielectric layer located on the upper surface of the semiconductor base layer and located on the upper sidewall surface of the trench.
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公开(公告)号：US20220262947A1
公开(公告)日：2022-08-18
申请号：US17735899
申请日：2022-05-03
Inventor： Bing Wu , Chien Ling Chan , Liang Tong
IPC: H01L29/78 , H01L29/66 , H01L29/10 , H01L29/40 , H01L29/08 , H01L21/265 , H01L21/3213 , H01L21/308 , H01L29/417 , H01L29/06 , H01L21/266
Abstract: An LDMOS transistor and a method for manufacturing the same are provided. The method includes: forming an epitaxial layer on a substrate, forming a gate structure on an upper surface of the epitaxial layer, forming a body region and a drift region in the epitaxial layer, forming a source region in the body region, forming a first insulating layer on the gate structure and an upper surface of the epitaxial layer and, forming a shield conductor layer on the first insulating layer, forming a second insulating layer covering the shield conductor layer, forming a first conductive path, to connect the source region with the substrate, and forming a drain region in the drift region. By forming the first conductive path which connects the source region with the substrate, the size of the LDMOS transistor and the resistance can be reduced.
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公开(公告)号：US20240317805A9
公开(公告)日：2024-09-26
申请号：US18343599
申请日：2023-06-28
Inventor： Ji Hoon Hong
Abstract: The present disclosure relates to a wafer level chip scale package with a rhombus shape which includes a semiconductor chip with a rhombus shape and a solder ball array including a plurality of solder balls formed on one surface of the semiconductor chip. Among four interior angles of the semiconductor chip, two of the four interior angles facing each other in a short diagonal direction are approximately 120°, and two of the four interior angles facing each other in a long diagonal direction are approximately 60°.
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公开(公告)号：US20240266937A1
公开(公告)日：2024-08-08
申请号：US18403203
申请日：2024-01-03
Inventor： Jin Wook Choi , Seok Won Choi , Jung Su Choi , Gi Chur Bae
CPC classification number: H02M1/0009 , H02M3/158
Abstract: A switching converter equipped with an adaptive frequency control function includes a switching unit, an inductor, an output capacitor, a zero crossing detector that receives a signal of the switching node and a signal of the output terminal, that are fed back, and detects whether or not an inductor current flowing through the inductor crosses a zero point, a DCM/CCM detector that outputs an operation section discrimination signal that discriminates a current operation section by dividing the current operation section into a discontinuous conduction mode (DCM) operation section and a continuous conduction mode (CCM) operation section according to a zero crossing detection signal output by the zero crossing detector, a variable oscillator that changes and outputs a clock frequency signal according to the operation section discrimination signal output by the DCM/CCM detector, and a controller that controls switching of switches constituting the switching unit according to the clock frequency signal output by the variable oscillator.
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公开(公告)号：US20240234536A9
公开(公告)日：2024-07-11
申请号：US18398686
申请日：2023-12-28
Inventor： Jiakun Wang , Hui Chen
CPC classification number: H01L29/66068 , H01L21/0465 , H01L21/047 , H01L29/7827 , H01L29/1095
Abstract: Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.
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