公开(公告)号：US12230628B2

公开(公告)日：2025-02-18

申请号：US18053722

申请日：2022-11-08

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/07 ,  H01L27/02 ,  H01L21/265 ,  H01L21/266

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

公开(公告)号：US12224318B2

公开(公告)日：2025-02-11

申请号：US17669479

申请日：2022-02-11

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chloe Hawes ,  Jennifer Gao ,  Scott Sheppard

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/778

Abstract: A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer. A gate finger and first and second source/drain contacts are provided on the semiconductor layer structure. A first source/drain region is provided in the semiconductor layer structure that includes a first implanted region that is underneath the first source/drain contact and a first auxiliary implanted region. A depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region. The first source/drain region extends inwardly a first distance from a lower edge of an inner sidewall of the first source/drain contact, and extends outwardly a second smaller distance from a lower edge of an outer sidewall of the first source/drain contact.

公开(公告)号：US20250048724A1

公开(公告)日：2025-02-06

申请号：US18921317

申请日：2024-10-21

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US20250031407A1

公开(公告)日：2025-01-23

申请号：US18715087

申请日：2022-03-07

Applicant: KOREA ELECTROTECHNOLOGY RESEARCH INSTITUTE

Inventor： Hyoung Woo KIM ,  Jeong Hyun MOON ,  Wook BAHNG ,  Jae Hwa SEO

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: A SiC semiconductor device having high pressure resistance properties is disclosed. The present invention provides a SiC semiconductor device comprising: a SiC substrate having a first surface and a second surface; an insulating area formed on the second surface side inside the SiC substrate; and a plurality of semiconductor areas including a source area, a base area, and a drain area formed along the first surface on the insulating area, wherein the SiC semiconductor device has a P/N junction parallel to the first surface, the P/N junction extending from the base area toward the drain area on the insulating area and being formed by a first auxiliary region of a first conductive type which is the same conductive type as the source area and a second auxiliary region of a second conductive type which is opposed to the first conductive type.

公开(公告)号：US20250022949A1

公开(公告)日：2025-01-16

申请号：US18238057

申请日：2023-08-25

Applicant: LX Semicon Co., Ltd.

Inventor： Seungwook SONG ,  Namju KANG ,  Jinok PARK ,  Doohyung LEE ,  Chaedeok LEE

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/66 ,  H02M7/537

Abstract: A power semiconductor device includes a substrate, a first conductivity type epitaxial layer disposed on the substrate, a second conductivity type well partially disposed on the first conductivity type epitaxial layer, a second conductivity type ion implantation region partially disposed in the second conductivity type well, a source region partially disposed in the second conductivity type well and disposed on the second conductivity type ion implantation region, a gate insulating layer disposed on the source region and the second conductive type well, a gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate, and a source electrode disposed on the source region. The gate insulating layer may include a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness thicker than the first thickness, A concentration in a Rb region which is a lateral resistance of the second conductivity type ion implantation region may be higher than that of the second conductivity type well.

公开(公告)号：US20250006784A1

公开(公告)日：2025-01-02

申请号：US18886108

申请日：2024-09-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Subhash Srinivas PIDAPARTHI ,  Andrew P. EDWARDS ,  Clifford DROWLEY ,  Kedar PATEL

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/40

Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.

公开(公告)号：US20240405065A1

公开(公告)日：2024-12-05

申请号：US18677905

申请日：2024-05-30

Applicant: HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： Chia-Lung HUNG ,  Yi-Kai HSIAO ,  Hao-Chung KUO

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device is provided, including: forming a first conductive type lightly doped region in the epitaxial layer; forming a first conductive type heavily doped region and a second conductive type heavily doped region in the epitaxial layer on the first conductive type lightly doped region, in which the neighboring first conductive type heavily doped regions are spaced apart by the second conductive type heavily doped region; disposing the mask on the second conductive type heavily doped region; disposing a spacer on a sidewall of the mask; doping a first conductive type dopant in the first conductive type lightly doped region to form an anti-breakdown region; removing the mask and forming a trench extending into the second conductive type heavily doped region, first conductive type lightly doped region and the epitaxial layer; and removing the spacer.

公开(公告)号：US20240405015A1

公开(公告)日：2024-12-05

申请号：US18336707

申请日：2023-06-16

Applicant: HeFeChip Corporation Limited

Inventor： Geeng-Chuan CHERN

IPC: H01L27/02 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device with ESD protection structure and a method of making it are disclosed. The semiconductor device with ESD protection structure includes at least one gate and source and drain regions on opposite sides of the at least one gate that constitute at least a discharging MOSFET. The gate includes first gate portions having a first dopant concentration and a second gate portion having a second dopant concentration. The first dopant concentration is lower than the second dopant concentration. The at least one first gate portions are lower portions of the gate above the edges of an active area, and the second gate portion is the remaining portion of the at least one gate other than the first gate portions.

公开(公告)号：US20240371974A1

公开(公告)日：2024-11-07

申请号：US18779097

申请日：2024-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHUN HSIUNG TSAI ,  KUO-FENG YU ,  YU-MING LIN ,  CLEMENT HSINGJEN WANN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/08

Abstract: A method of manufacturing a semiconductor device includes: depositing a first dielectric layer and a second dielectric layer over a substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; removing the dummy gate electrode and forming a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate; and performing a first treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the substrate, the LDD regions and the ILD layer.

公开(公告)号：US20240363435A1

公开(公告)日：2024-10-31

申请号：US18766003

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure provides a method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area, forming a first active region in the first circuit area and a second active region on the second circuit area, forming first gate stacks on the first active region and second gate stacks on the second active region, performing a plurality of implantation processes to introduce a doping species to the first active region with a first dosage and to the second active region with a second dosage different from the first dosage, and forming first source/drain features within first source/drain regions of the first active region and second source/drain features within second source/drain regions of the second active region.