公开(公告)号：US20240363698A1

公开(公告)日：2024-10-31

申请号：US18139017

申请日：2023-04-25

申请人： Nami MOS CO., LTD.

发明人： FU-YUAN HSIEH ,  LIN XU

IPC分类号： H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/407 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/7813

摘要： A SiC shielded gate trench device having a first type gate trench and a second type gate trench is disclosed. The first type gate trench is above the second type gate trench and has a trench width wider than a trench width of the second type gate trench, wherein the first type gate trench is filled with a gate electrode and a shielded gate electrode, and a grounded P-shield region surrounding the second type gate trench is under the shielded gate electrode for gate oxide electric-field reduction. The device further comprises a current spreading region surrounding the gate electrode for on-resistance reduction.

公开(公告)号：US20240363689A1

公开(公告)日：2024-10-31

申请号：US18761779

申请日：2024-07-02

申请人： Samsung Electronics Co., Ltd.

发明人： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC分类号： H01L29/10 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1037 ,  H01L21/02568 ,  H01L29/408 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/66795 ,  H01L29/785

摘要： Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US12132082B2

公开(公告)日：2024-10-29

申请号：US17871464

申请日：2022-07-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pei-Wei Lee ,  Yasutoshi Okuno ,  Pang-Yen Tsai

IPC分类号： H01L21/02 ,  H01L21/66 ,  H01L29/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1037 ,  H01L22/12 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.

公开(公告)号：US12125918B2

公开(公告)日：2024-10-22

申请号：US17182270

申请日：2021-02-23

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei Yamazaki

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/786

CPC分类号： H01L29/7869 ,  H01L29/1054 ,  H01L29/78696

摘要： A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.

公开(公告)号：US12125906B2

公开(公告)日：2024-10-22

申请号：US17563141

申请日：2021-12-28

申请人： DENSO CORPORATION

发明人： Shinichiro Yanagi ,  Yusuke Nonaka ,  Syogo Ikeura

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

CPC分类号： H01L29/7824 ,  H01L29/0653 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/404

摘要： In a semiconductor device having a lateral transistor, a source wiring layer is disposed above at least a part of an interlayer insulating film. The interlayer insulating film is electrically connected to a source electrode and is extended toward a drain region to form a source field plate.

公开(公告)号：US12125901B2

公开(公告)日：2024-10-22

申请号：US18091807

申请日：2022-12-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Makoto Shimosawa

IPC分类号： H01L29/739 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7397 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/02271 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/7813

摘要： Semiconductor device including first semiconductor layer of a first conductivity type, second semiconductor layer of a second conductivity type at a surface of the first semiconductor layer, third semiconductor layer of the first conductivity type selectively provided at a surface of the second layer, and gate electrode embedded in a trench via a gate insulating film. The trench penetrates the second and third layers, and reaches the first layer. A thermal oxide film on the third layer has a thickness less than that of the gate insulating film. Also are an interlayer insulating film on the thermal oxide film, barrier metal on an inner surface of a contact hole selectively opened in the thermal oxide film and the interlayer insulating film, metal plug embedded in the contact hole on the barrier metal, and electrode electrically connected to the second and third layers via the barrier metal and the metal plug.

公开(公告)号：US20240347638A1

公开(公告)日：2024-10-17

申请号：US18301382

申请日：2023-04-17

申请人： GlobalFoundries U.S. Inc.

发明人： Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette ,  James P. Mazza ,  Hong Yu

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/28123 ,  H01L29/1037 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66795

摘要： Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.

公开(公告)号：US12119393B2

公开(公告)日：2024-10-15

申请号：US17847448

申请日：2022-06-23

申请人： Adeia Semiconductor Solutions LLC

发明人： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/66 ,  H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/311 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/66803 ,  H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76895 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

公开(公告)号：US20240339534A1

公开(公告)日：2024-10-10

申请号：US18746063

申请日：2024-06-18

申请人： UNITED MICROELECTRONICS CORP.

发明人： Che-Hua Chang ,  Shin-Hung Li ,  Tsung-Yu Yang ,  Ruei-Jhe Tsao

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7825 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/66704

摘要： A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.

公开(公告)号：US12113121B2

公开(公告)日：2024-10-08

申请号：US17887703

申请日：2022-08-15

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Ming-Yeh Chuang

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66803 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/7856

摘要： A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.