公开(公告)号：US12176397B2

公开(公告)日：2024-12-24

申请号：US17567399

申请日：2022-01-03

Applicant: Nami MOS CO. LTD.

Inventor： Fu-Yuan Hsieh

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/78

Abstract: The present invention introduces a new shielded gate trench SBR (Super Barrier Rectifier) wherein an epitaxial layer having special MSE (multiple stepped epitaxial) layers with different doping concentrations decreasing in a direction from a substrate to a top surface of the epitaxial layer, wherein each of the MSE layers has an uniform doping concentration as grown. Forward voltage Vf is significantly reduced with the special MSE layers. An integrated circuit comprising a SGT MOSFET and a SBR formed on a single chip obtains benefits of low on-resistance, low reverse recovery time and high avalanche capability from the special MSE layers.

公开(公告)号：US20240347607A1

公开(公告)日：2024-10-17

申请号：US18135485

申请日：2023-04-17

Applicant: Nami MOS CO., LTD.

Inventor： FU-YUAN HSIEH ,  LIN XU

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L29/407 ,  H01L29/0634 ,  H01L29/7813 ,  H01L29/8725

Abstract: A SGT MOSFET and a SGT super barrier rectifier having improved on-resistance and gate charge structures are disclosed in this invention by applying a short channel implant region for formation of a shorter channel length after body implantation and diffusion, and by introducing a super junction region below an oxide charge balance region for breakdown voltage enhancement. The present invention can further achieve a lower specific on-resistance by applying multiple stepped epitaxial layers or multiple stepped oxide structure.

公开(公告)号：US20230327013A1

公开(公告)日：2023-10-12

申请号：US17715089

申请日：2022-04-07

Applicant: Nami MOS CO., LTD.

Inventor： FU-YUAN HSIEH

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/7811

Abstract: The present invention introduces a new shielded gate trench MOSFETs with improved specific on-resistance and avalanche capability structures including an active area and an edge termination area, wherein an epitaxial layer having special multiple stepped epitaxial (MSE) layers in an oxide charge balance (OCB) region, and an edge termination having multiple trench field plates, and electric field reducing regions disposed surrounding bottom of gate trenches with a doping concentration lower than said bottom epitaxial layer of the MSE layers. Moreover, in some preferred embodiment, a multiple stepped oxide structure in the OCB region, and an epitaxial layer in a buffer region below the OCB region with a doping concentration lower than the MSE layers is introduced to further reduce the specific on-resistance and enhance device ruggedness.

公开(公告)号：US20220231167A1

公开(公告)日：2022-07-21

申请号：US17716123

申请日：2022-04-08

Applicant: NAMI MOS CO., LTD.

Inventor： Fu-Yuan HSIEH

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/40 ,  H01L29/49 ,  H01L29/866

Abstract: A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

公开(公告)号：US11380787B2

公开(公告)日：2022-07-05

申请号：US16869659

申请日：2020-05-08

Applicant: Nami MOS CO., LTD.

Inventor： Fu-Yuan Hsieh

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: An integrated circuit comprising an SGT MOSFET and a short channel SBR is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel for switching loss reduction. Only one additional mask is required for integration of the short channel SBR having thinner gate oxide than the SGT MOSFET. Moreover, in some preferred embodiment, an MSO structure is applied to the shielded gate structure to further reduce the on-resistance.

公开(公告)号：US20210296488A1

公开(公告)日：2021-09-23

申请号：US16823376

申请日：2020-03-19

Applicant: Nami MOS CO., LTD.

Inventor： Fu-Yuan HSIEH

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: A trenched semiconductor power device is disclosed comprising a plurality of trenched gates, each including a gate electrode and a shielded gate electrode forming an oxide charge balance region between adjacent trenched gates; and the trenched semiconductor power device further comprises a super junction structure including a plurality of alternating P and N regions disposed above a substrate and forming a junction charge balance region below the oxide charge balance region for breakdown voltage enhancement, on-resistance and output capacitance reductions.

公开(公告)号：US20210104624A1

公开(公告)日：2021-04-08

申请号：US16594133

申请日：2019-10-07

Applicant: Nami MOS CO., LTD.

Inventor： Fu-Yuan HSIEH

IPC: H01L29/78 ,  H01L29/788 ,  H01L29/40

Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of multiple trench MOSFETs connected together with multiple sawing trenched gates across a space between two trench MOSFETs having a width same as scribe line. Dummy cells formed between an edge trench and active area act as butler cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

公开(公告)号：US20210104510A1

公开(公告)日：2021-04-08

申请号：US16590609

申请日：2019-10-02

Applicant: Nami MOS CO., LTD.

Inventor： Fu-Yuan HSIEH

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40

Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching.

公开(公告)号：US20240395877A1

公开(公告)日：2024-11-28

申请号：US18202400

申请日：2023-05-26

Applicant: Nami MOS CO., LTD.

Inventor： FU-YUAN HSIEH ,  LIN XU

IPC: H01L29/40 ,  H01L21/265 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

Abstract: Shielded gate devices having a planarized thermally grown (PTG) inter-poly oxide (IPO) structure are disclosed. By using a method having double wet etching processes of a field oxide and double dry etching processes of a first doped polysilicon, the PTG IPO structure is achieved to reduce gate-source leakage current Igss and gate resistance Rg. A gate oxide and a PTG IPO are thermally grown simultaneously. The devices further comprise a current spreading region surrounding a lower portion of a gate electrode for on-resistance reduction.

公开(公告)号：US20240128369A1

公开(公告)日：2024-04-18

申请号：US17964172

申请日：2022-10-12

Applicant: Nami MOS CO., LTD.

Inventor： FU-YUAN HSIEH

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/7811

Abstract: Shielded gate trench MOSFETs with gate trenches separated from termination trenches are disclosed, wherein a first type body regions are formed in an active area and an first type electric field reducing regions formed adjacent to an intersection regions between a first termination trench and trench ends of gate trenches; The first type electric field reducing regions formed between the first type body regions and the first termination trench wherein the first type body regions are absent to enhance breakdown voltage. At least one second type body region of the second conductivity type with a floating voltage is formed within the first type field reducing regions, and is spaced apart from the first type body regions and the first termination trench for further increasing breakdown voltage.