公开(公告)号：US20240363734A1

公开(公告)日：2024-10-31

申请号：US18770088

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  Ling-Sung Wang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/28088 ,  H01L21/76877 ,  H01L21/82345 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

公开(公告)号：US20240363721A1

公开(公告)日：2024-10-31

申请号：US18771578

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chin CHANG ,  Ming-Huan TSAI ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

公开(公告)号：US20240363712A1

公开(公告)日：2024-10-31

申请号：US18505279

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Moon Lee ,  Jin Bum Kim ,  Hyo Jin Kim ,  Yong Jun Nam ,  In Geon Hwang

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate, an active pattern extended in a first horizontal direction on the substrate, a plurality of nanosheets stacked and spaced apart from each other in a vertical direction on the active pattern, a gate electrode extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern, a gate insulating layer between the plurality of nanosheets and the gate electrode, and a doping layer between the plurality of nanosheets and the gate insulating layer, the doping layer including silicon (Si) or silicon germanium (SiGe) and doped with a doping material, at least a portion of the doping layer overlapping an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.

公开(公告)号：US20240363709A1

公开(公告)日：2024-10-31

申请号：US18770563

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

公开(公告)号：US20240363685A1

公开(公告)日：2024-10-31

申请号：US18507839

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Jun LIM ,  Tae Ho CHA ,  Su Bin LEE ,  Jeong Hyeon LEE ,  Hak Jong LEE ,  Seung Hyeon HONG

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: an active pattern including a lower pattern and sheet patterns spaced apart from the lower pattern in a first direction; gate structures being separate in a second direction on the lower pattern. The gate structure includes a gate electrode and a gate insulating layer; a source/drain recess between the gate structures adjacent to each other; and a source/drain pattern filling the source/drain recess. The source/drain pattern includes: a first epitaxial region extended along a sidewall and a bottom surface of the source/drain recess, a second epitaxial region on the first epitaxial insertion epitaxial regions that are in contact with the first epitaxial region. The respective insertion epitaxial regions are spaced apart from each other and include silicon germanium. The first epitaxial region is disposed between the second epitaxial region and the insertion epitaxial region.

公开(公告)号：US12132105B2

公开(公告)日：2024-10-29

申请号：US17571949

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Choi ,  Ji Seong Kim ,  Min Cheol Oh ,  Ki-Il Kim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66666

Abstract: There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.

公开(公告)号：US20240355934A1

公开(公告)日：2024-10-24

申请号：US18304659

申请日：2023-04-21

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Tristan A. Tronic ,  Jennifer Lux ,  Uygar E. Avci ,  Kevin P. O'Brien

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66969 ,  H01L29/0847 ,  H01L29/24

Abstract: Described herein are transistors with monolayer transition metal dichalcogenides (TMD) semiconductor material. TMD materials include combination of a transition metal (e.g., molybdenum or tungsten) and a chalcogen (e.g., sulfur or selenium) in a monolayer having a hexagonal crystal structure. A transistor has a single layer of TMD forming a channel region, and multiple layers of the TMD material at the source and drain regions. Upper portions of the multilayer TMD source and drain regions are doped, and conductive contacts are formed over the doped portions.

公开(公告)号：US12125891B2

公开(公告)日：2024-10-22

申请号：US17244430

申请日：2021-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Liang Lu ,  Chang-Yin Chen ,  Chih-Han Lin ,  Chia-Yang Liao

IPC: H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

公开(公告)号：US12125879B2

公开(公告)日：2024-10-22

申请号：US18360495

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chun-An Lin ,  Wei-Yuan Lu ,  Guan-Ren Wang ,  Peng Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

公开(公告)号：US20240347611A1

公开(公告)日：2024-10-17

申请号：US18750737

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ding-Kang Shih ,  Sung-Li Wang ,  Pang-Yen Tsai

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76202 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/785 ,  H01L21/823871 ,  H01L29/665 ,  H01L29/66545

Abstract: Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.