公开(公告)号：US20240347392A1

公开(公告)日：2024-10-17

申请号：US18753130

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L21/285 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L21/28568

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US20240339448A1

公开(公告)日：2024-10-10

申请号：US18748008

申请日：2024-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chih YU ,  Chien-Mao CHEN

IPC: H01L27/06 ,  H01C7/00 ,  H01C17/14 ,  H01L21/8238 ,  H01L27/01

CPC classification number: H01L27/0629 ,  H01C7/006 ,  H01C17/14 ,  H01L21/823878 ,  H01L27/016 ,  H01L28/24 ,  H01L21/823842

Abstract: A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.

公开(公告)号：US12107144B2

公开(公告)日：2024-10-01

申请号：US17574329

申请日：2022-01-12

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/45 ,  H01L21/265 ,  H01L21/66 ,  H01L21/8238 ,  H01L29/41 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L22/12 ,  H01L29/413 ,  H01L29/456 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4975 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

公开(公告)号：US12082389B2

公开(公告)日：2024-09-03

申请号：US18320494

申请日：2023-05-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon Jhy Liaw

IPC: H10B10/00 ,  G11C11/419 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H10B10/125 ,  G11C11/419 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor structure includes first and second SRAM cells disposed over a substrate. Each first SRAM cell includes at least two first p-type transistors and four first n-type transistors. Each first p-type and n-type transistors includes a channel in a single semiconductor fin. Each second SRAM cell includes at least two second p-type transistors and four second n-type transistors. Each second p-type transistors includes a channel in a single semiconductor fin. Each second n-type transistors includes a channel in multiple semiconductor fins. The source/drain regions of the first p-type transistors are doped at a first dopant concentration, the source/drain regions of the second p-type transistors are doped at a second dopant concentration, and the first dopant concentration is greater than the second dopant concentration.

公开(公告)号：US20240274476A1

公开(公告)日：2024-08-15

申请号：US18644657

申请日：2024-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chi On Chui ,  Fang-Yi Liao ,  Chunyao Wang ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

公开(公告)号：US20240250140A1

公开(公告)日：2024-07-25

申请号：US18531030

申请日：2023-12-06

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Krishna Kumar Bhuwalka

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor architecture includes a substrate, an n-type transistor, and a p-type transistor, each formed on the substrate. Each of the n-type transistor and the p-type transistor of the semiconductor architecture includes a plurality of finger sub-devices, and each finger sub-device of the plurality of finger sub-devices includes a plurality of stacked semiconductors. One or more of the finger sub-devices of the plurality of finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device including a dielectric barrier that extends down only one side of the stacked semiconductors.

公开(公告)号：US12033900B2

公开(公告)日：2024-07-09

申请号：US17815094

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Yuh-Ta Fan ,  Tien-Wei Yu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/32134 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966

Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.

公开(公告)号：US20240204102A1

公开(公告)日：2024-06-20

申请号：US18536880

申请日：2023-12-12

Applicant: Sony Group Corporation

Inventor： Yasushi Tateshita

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42312 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836 ,  H01L29/7845 ,  H01L21/28079

Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

公开(公告)号：US12015030B2

公开(公告)日：2024-06-18

申请号：US17705944

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Donald Y. Chao ,  Yi-Shien Mor ,  Kuo-Tai Huang

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.

公开(公告)号：US20240186397A1

公开(公告)日：2024-06-06

申请号：US18173818

申请日：2023-02-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chen Chang ,  Anhao Cheng ,  Meng-I Kang ,  Yen-Liang Lin

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28123 ,  H01L27/092 ,  H01L29/4966

Abstract: In accordance with some aspects of the disclosure, a semiconductor structure is provided. The semiconductor structure includes: an active region; and a gate stack disposed on the active region. The gate stack includes: at least one gate dielectric layer disposed on the active region; and a metal gate structure disposed on the at least one gate dielectric layer. The metal gate structure includes: a metal gate layer comprising a first material; and at least one dummy structure disposed in the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material. The second material is different from the first material.