公开(公告)号：US20240213132A1

公开(公告)日：2024-06-27

申请号：US18089476

申请日：2022-12-27

申请人： Intel Corporation

发明人： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Darko GRUJICIC ,  Shayan KAVIANI ,  Mahdi MOHAMMADIGHALENI ,  Suddhasattwa NAD ,  Thomas L. SOUNART ,  Marcel WALL ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC分类号： H01L23/498 ,  H01L27/01

CPC分类号： H01L23/49838 ,  H01L27/016 ,  H01L28/86 ,  H01L28/90 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16

摘要： Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.

公开(公告)号：US11978825B2

公开(公告)日：2024-05-07

申请号：US17388949

申请日：2021-07-29

申请人： Apple Inc.

发明人： Kelly McGroddy ,  Hsin-Hua Hu ,  Andreas Bibl ,  Clayton Ka Tsun Chan ,  Daniel Arthur Haeger

IPC分类号： H01L33/14 ,  H01L23/00 ,  H01L25/075 ,  H01L27/01 ,  H01L27/15 ,  H01L33/00 ,  H01L33/06 ,  H01L33/30 ,  H01L33/42 ,  G09G3/32 ,  H01L33/16 ,  H01L33/20

CPC分类号： H01L33/145 ,  H01L24/75 ,  H01L24/95 ,  H01L25/0753 ,  H01L27/016 ,  H01L27/156 ,  H01L33/0093 ,  H01L33/06 ,  H01L33/14 ,  H01L33/30 ,  H01L33/42 ,  G09G3/32 ,  H01L33/0016 ,  H01L33/0095 ,  H01L33/16 ,  H01L33/20 ,  H01L2224/75305 ,  H01L2224/75725 ,  H01L2224/7598 ,  H01L2224/82203 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.

公开(公告)号：US20240105707A1

公开(公告)日：2024-03-28

申请号：US18188294

申请日：2023-03-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Fu-Chiang Kuo ,  Meei-Shiou Chern ,  Jyun-Ting Hou

IPC分类号： H01L27/01 ,  H01L21/762 ,  H01L21/84

CPC分类号： H01L27/016 ,  H01L21/76283 ,  H01L21/84

摘要： Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a trench extending into a substrate, in a top view, the trench extends lengthwise along a first direction, forming a material layer over the substrate and intersecting a first portion of the trench, after the forming of material layer, forming a first capacitor intersecting a second portion of the trench, the first capacitor comprising a first plurality of conductor plates, and forming a second capacitor intersecting a third portion of the trench, the second capacitor comprising a second plurality of conductor plates, where the first plurality of conductor plates and the second plurality of conductor plates are in direct contact with the material layer.

公开(公告)号：US20240072032A1

公开(公告)日：2024-02-29

申请号：US17894043

申请日：2022-08-23

申请人： QUALCOMM Incorporated

发明人： Yanmei SONG ,  William STONE ,  Jianwen XU ,  Senthil SIVASWAMY ,  John HOLMES ,  Ryan LANE

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/016 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/224 ,  H01L2224/24155 ,  H01L2224/73209 ,  H01L2224/81815 ,  H01L2224/821 ,  H01L2224/92124 ,  H01L2225/06513 ,  H01L2225/06524

摘要： A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

公开(公告)号：US11840756B2

公开(公告)日：2023-12-12

申请号：US17066670

申请日：2020-10-09

申请人： University of North Texas

发明人： Santanu Das ,  Sundeep Mukherjee

IPC分类号： H01L23/52 ,  C23C14/35 ,  C23C14/54 ,  C22C5/08 ,  C23C14/18 ,  C23C14/14 ,  C23C14/08 ,  H01L27/01

CPC分类号： C23C14/35 ,  C22C5/08 ,  C23C14/087 ,  C23C14/14 ,  C23C14/185 ,  C23C14/542 ,  H01L23/52 ,  H01L27/016

摘要： An interconnect and a method of making an interconnect between one or more features on a substrate comprises: sputtering a noble metal-copper eutectic thin film under controlled power on an oxide grown or deposited on a substrate; and forming an amorphous alloy structure from the noble metal-copper eutectic thin film in the shape of the interconnect and the interconnect comprising no grain or grain boundaries without temperature sensitive resistivity.

公开(公告)号：US11728265B2

公开(公告)日：2023-08-15

申请号：US16129711

申请日：2018-09-12

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian ,  Dilan Seneviratne ,  Yonggang Li ,  Sameer Paital ,  Darko Grujicic ,  Rengarajan Shanmugam ,  Melissa Wette ,  Srinivas Pietambaram

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00 ,  H01L27/01 ,  H01L23/64

CPC分类号： H01L23/5228 ,  H01L21/4846 ,  H01L21/76871 ,  H01L23/498 ,  H01L23/5226 ,  H01L23/647 ,  H01L24/09 ,  H01L27/016 ,  H01L28/24

摘要： Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

公开(公告)号：US20230197351A1

公开(公告)日：2023-06-22

申请号：US17557572

申请日：2021-12-21

申请人： Chong ZHANG ,  Cheng XU ,  Junnan ZHAO ,  Ying WANG ,  Meizi JIAO

发明人： Chong ZHANG ,  Cheng XU ,  Junnan ZHAO ,  Ying WANG ,  Meizi JIAO

IPC分类号： H01G4/33 ,  H01G4/008 ,  H01G4/12 ,  H01G4/224 ,  H01L49/02 ,  H01L27/01

CPC分类号： H01G4/33 ,  H01G4/008 ,  H01G4/224 ,  H01G4/1209 ,  H01L27/016 ,  H01L28/75

摘要： Embodiments herein relate to systems, apparatuses, or processes directed to packages that include one or more glass cores that have thin film capacitors on one or more sides of the one or more glass cores. The film capacitors may be formed in-situ on the glass cores during substrate manufacturing. Other embodiments may be described and/or claimed.

公开(公告)号：US20190252365A1

公开(公告)日：2019-08-15

申请号：US16387484

申请日：2019-04-17

申请人： InnoLux Corporation

发明人： Jia-Yuan Chen ,  Hsiao-Lang Lin ,  Jui-Jen Yueh ,  Kuan-Feng Lee

IPC分类号： H01L27/01 ,  H01L29/786 ,  G02F1/133 ,  G02F1/1333 ,  H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L27/12 ,  H01L51/52 ,  H01L51/00 ,  G02F1/153 ,  G02F1/1347 ,  G02F1/1343

CPC分类号： H01L27/016 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133308 ,  G02F1/1343 ,  G02F1/1347 ,  G02F1/1533 ,  H01L27/0218 ,  H01L27/1251 ,  H01L27/32 ,  H01L27/3244 ,  H01L29/0653 ,  H01L29/41733 ,  H01L29/786 ,  H01L51/0097 ,  H01L51/5256 ,  H01L2251/5338 ,  Y10T428/10

摘要： A display device includes a light-emitting unit and a light conversion layer disposed on the light-emitting unit. The light conversion layer includes plural quantum dot portions and a first shielding portion surrounding the plural quantum dot portions. One of the plural quantum dot portions has a surface, and at least a part of the surface is a curved surface. A first thickness of the first shielding portion is greater than a maximum thickness of one of the plural quantum dot portions.

公开(公告)号：US20180367114A1

公开(公告)日：2018-12-20

申请号：US15950886

申请日：2018-04-11

申请人： Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

发明人： Dror Hurwitz ,  Alex Huang

IPC分类号： H03H7/01 ,  H03H3/00 ,  H01L27/01 ,  H01L49/02 ,  H03H1/00

CPC分类号： H03H7/0138 ,  H01L27/016 ,  H01L28/10 ,  H01L28/60 ,  H03H3/00 ,  H03H7/0115 ,  H03H2001/0085

摘要： A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the ceramic dielectric layer, and forms an upper electrode whose capacitance is proportional to the area of the via post forming the upper electrode, and wherein the at least one inductor is formed in at least one of the at least one feature layer and the adjacent via layer by electroplating copper into a pattern of photoresist stripping away the photoresist and laminating.

公开(公告)号：US20180295747A1

公开(公告)日：2018-10-11

申请号：US15912522

申请日：2018-03-05

申请人： GETAC TECHNOLOGY CORPORATION

发明人： Chi-Jung Wu

IPC分类号： H05K7/20 ,  F25D5/00 ,  F28F21/08 ,  H05K7/14

CPC分类号： H05K7/20481 ,  F25D5/00 ,  F28F21/084 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/3737 ,  H01L27/016 ,  H05K7/1404 ,  H05K7/20472

摘要： An edge sealing heat-dissipating film includes a heat radiation emitting film, a metal film and a heat radiation receiving film. The heat radiation emitting film has a first opening. The metal film is disposed to the heat radiation emitting film and the metal film has a second opening. The second opening is positioned corresponding to the first opening. The heat radiation receiving film is disposed to the metal film and the heat radiation receiving film has a third opening. Wherein, the shape of the heat radiation emitting film is the same as the shape of the heat radiation receiving film. And the area of the metal film is slightly smaller than the area of the heat radiation receiving film and the heat radiation emitting film. Therefore, the outer periphery of the heat radiation emitting film and the outer periphery of the heat radiation receiving film could be closely bonded together.