公开(公告)号：US20240222139A1

公开(公告)日：2024-07-04

申请号：US18090879

申请日：2022-12-29

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Brandon Marin ,  Gang Duan ,  Jeremy Ecton ,  Srinivas Pietambaram

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC分类号： H01L21/4842 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16258

摘要： Microelectronic integrated circuit package structures include a solder joint structure having a first portion on a die and a second portion on a substrate. The first portion comprises a first metal. An inner portion of the second portion comprises a second metal, and an outer portion of the second portion comprises an intermetallic compound (IMC) of the first and second metals.

公开(公告)号：US20240222035A1

公开(公告)日：2024-07-04

申请号：US18090305

申请日：2022-12-28

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Kristof Darmawikarta ,  Benjamin Duong ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Jason Steill ,  Thomas Sounart ,  Darko Grujicic

IPC分类号： H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC分类号： H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/165 ,  H01L23/3675

摘要： Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.

公开(公告)号：US20240219644A1

公开(公告)日：2024-07-04

申请号：US18090260

申请日：2022-12-28

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Benjamin Duong ,  Hiroki Tanaka ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram ,  Hari Mahalingam

IPC分类号： G02B6/35 ,  G02B6/42 ,  H01L23/498

CPC分类号： G02B6/35 ,  G02B6/4274 ,  H01L23/49816

摘要： An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240194657A1

公开(公告)日：2024-06-13

申请号：US18080152

申请日：2022-12-13

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC分类号： H01L25/16 ,  G02B6/42 ,  H01L21/56 ,  H01L23/00 ,  H01L23/433

CPC分类号： H01L25/167 ,  G02B6/4239 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4269 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/08 ,  H01L24/80 ,  G02B6/426 ,  H01L24/16 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/16225 ,  H01L2224/80895 ,  H01L2924/1431 ,  H01L2924/182

摘要： Apparatuses, systems, assemblies, and techniques related to integrating photonics integrated circuit devices and electronic integrated circuit devices into an assembly or module are described. An integrated module includes a photonics integrated circuit device within an opening of a glass core substrate and an electronic integrated circuit device direct bonded to the photonics integrated circuit device. An optical waveguide is within or on the glass core substrate and has a terminal end edge coupled to the photonics integrated circuit device within the opening.

公开(公告)号：US20240113075A1

公开(公告)日：2024-04-04

申请号：US17956363

申请日：2022-09-29

申请人： Intel Corporation

发明人： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC分类号： H01L25/065 ,  H01L21/52 ,  H01L23/538

CPC分类号： H01L25/0655 ,  H01L21/52 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389

摘要： Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

公开(公告)号：US20240112971A1

公开(公告)日：2024-04-04

申请号：US17957359

申请日：2022-09-30

申请人： Intel Corporation

发明人： Yiqun Bai ,  Dingying Xu ,  Srinivas Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Haobo Chen ,  Kyle Arrington ,  Bohan Shan

IPC分类号： H01L23/15 ,  H01L21/02 ,  H01L23/495

CPC分类号： H01L23/15 ,  H01L21/02354 ,  H01L23/49506

摘要： An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.

公开(公告)号：US20240006284A1

公开(公告)日：2024-01-04

申请号：US17855298

申请日：2022-06-30

申请人： Intel Corporation

发明人： Kristof Darmawikarta ,  Srinivas Pietambaram ,  Benjamin Duong ,  Haobo Chen

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/16 ,  H01L23/49894 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L23/5386

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices. An example apparatus includes an electrically conductive layer, a dielectric layer, and an electrically nonconductive layer separating the dielectric layer from the conductive layer, the nonconductive layer having a first surface facing the conductive layer and a second surface facing the dielectric layer, the first surface having a first roughness, the second surface having a second roughness greater than the first roughness.

公开(公告)号：US11855125B2

公开(公告)日：2023-12-26

申请号：US16560647

申请日：2019-09-04

申请人： Intel Corporation

发明人： Srinivas Pietambaram ,  Brandon C. Marin ,  Jeremy Ecton ,  Hiroki Tanaka ,  Frank Truong

IPC分类号： H01L21/48 ,  H01G4/008 ,  H01G4/28 ,  H01G4/12 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01G4/008 ,  H01G4/1209 ,  H01G4/28 ,  H01L21/4846

摘要： Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

公开(公告)号：US11780210B2

公开(公告)日：2023-10-10

申请号：US16574252

申请日：2019-09-18

申请人： Intel Corporation

发明人： Jieying Kong ,  Gang Duan ,  Srinivas Pietambaram ,  Patrick Quach ,  Dilan Seneviratne

IPC分类号： H01L21/00 ,  B32B17/10 ,  B32B15/20 ,  H01L23/00 ,  H01L23/48

CPC分类号： B32B17/10192 ,  B32B15/20 ,  H01L23/481 ,  H01L24/09 ,  H01L2224/02379

摘要： Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

公开(公告)号：US20220404553A1

公开(公告)日：2022-12-22

申请号：US17354446

申请日：2021-06-22

申请人： Intel Corporation

发明人： Ankur Agrawal ,  Benjamin Duong ,  Ravindranath Mahajan ,  Debendra Mallik ,  Srinivas Pietambaram

IPC分类号： G02B6/26

摘要： An integrated circuit package may be formed comprising a first integrated circuit assembly, a second integrated circuit assembly, and a means to transfer optical signals therebetween. This optical signal transfer may be facilitated with a first lens or a first micro-lens array adjacent at least one waveguide of the first integrated circuit assembly and a second lens or second micro-lens array adjacent at least one waveguide of the second integrated circuit assembly, wherein the optical signals are transmitted across a gap between the first lens/micro-lens array and the second lens/micro-lens array. In further embodiments, the optical signal transfer assembly may comprise at least one photonic bridge between at least one waveguide of the first integrated circuit assembly and at least one waveguide of the second integrated circuit assembly.