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1.发明公开公开(公告)号：US20230333998A1
公开(公告)日：2023-10-19
申请号：US18312752
申请日：2023-05-05
申请人： Intel Corporation
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Systems, apparatuses and methods may provide for technology that includes a plurality of memory engines corresponding to a plurality of pipelines, wherein each memory engine in the plurality of memory engines is adjacent to a pipeline in the plurality of pipelines, and wherein a first memory engine is to request one or more direct memory access (DMA) operations associated with a first pipeline, and a plurality of operation engines corresponding to a plurality of dynamic random access memories (DRAMs), wherein each operation engine in the plurality of operation engines is adjacent to a DRAM in the plurality of DRAMs, and wherein one or more of the plurality of operation engines is to conduct the one or more DMA operations based on one or more bitmaps.
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公开(公告)号：US20240241645A1
公开(公告)日：2024-07-18
申请号：US18621437
申请日：2024-03-29
申请人： Intel Corporation
发明人： Robert Pawlowski , Shruti Sharma , Fabio Checconi , Sriram Aananthakrishnan , Jesmin Jahan Tithi , Jordi Wolfson-Pou , Joshua B. Fryman
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0673
摘要： Systems, apparatuses and methods may provide for technology that includes a plurality of hash management buffers corresponding to a plurality of pipelines, wherein each hash management buffer in the plurality of hash management buffers is adjacent to a pipeline in the plurality of pipelines, and wherein a first hash management buffer is to issue one or more hash packets associated with one or more hash operations on a hash table. The technology may also include a plurality of hash engines corresponding to a plurality of dynamic random access memories (DRAMs), wherein each hash engine in the plurality of hash engines is adjacent to a DRAM in the plurality of DRAMs, and wherein one or more of the hash engines is to initialize a target memory destination associated with the hash table and conduct the one or more hash operations in response to the one or more hash packets.
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3.发明公开公开(公告)号：US20240119015A1
公开(公告)日：2024-04-11
申请号：US18458462
申请日：2023-08-30
申请人： Intel Corporation
发明人： Shruti Sharma , Robert Pawlowski
CPC分类号： G06F13/1673 , G06F9/526
摘要： Systems, apparatuses and methods may provide for technology that detects a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask, generates a combined read-lock request for the plurality of atomic instructions in response to the condition, and sends the combined read-lock request to a lock buffer coupled to a memory device associated with the common address.
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4.发明公开公开(公告)号：US20240020253A1
公开(公告)日：2024-01-18
申请号：US18477787
申请日：2023-09-29
申请人： Intel Corporation
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F2213/28
摘要： Systems, apparatuses and methods may provide for technology that detects a plurality of sub-instruction requests from a first memory engine in a plurality of memory engines, wherein the plurality of sub-instruction requests are associated with a direct memory access (DMA) data type conversion request from a first pipeline, wherein each sub-instruction request corresponds to a data element in the DMA data type conversion request, and wherein the first memory engine is to correspond to the first pipeline, decodes the plurality of sub-instruction requests to identify one or more arguments, loads a source array from a dynamic random access memory (DRAM) in a plurality of DRAMs, wherein the operation engine is to correspond to the DRAM, and conducts a conversion of the source array from a first data type to a second data type in accordance with the one or more arguments.
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公开(公告)号：US20240256283A1
公开(公告)日：2024-08-01
申请号：US18566068
申请日：2022-03-31
申请人： Intel Corporation
发明人： Joshua B. Fryman , Byoungchan Oh , Sai Dheeraj Polagani , Kevin P. Ma , Robert S. Pawlowski , Bharadwaj Coimbatore Krishnamurthy , Shruti Sharma , Smitha P. Vasantha Kumar , Jason Howard , Daniel S. Klowden
CPC分类号： G06F9/3851 , G06F11/3409
摘要： A system is provided that includes a set of graph processing cores and a set of dense compute cores. where the set of graph processing cores and the set of dense cores are interconnected in a network. The dense compute cores include offload queue circuitry to receive an offload request from the set of graph processing cores to handle dense compute workloads. Memory controllers are also provided in the system for use by the graph processing cores in reading and writing to memory in association with sparse graph applications. the memory controllers enhanced to efficiently handle memory transactions in sparse graph applications.
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6.发明公开公开(公告)号：US20230315451A1
公开(公告)日：2023-10-05
申请号：US18326623
申请日：2023-05-31
申请人： Intel Corporation
CPC分类号： G06F9/30043 , G06F9/30079 , G06F13/28
摘要： Systems, apparatuses and methods may provide for technology that detects, by an operation engine, a plurality of sub-instruction requests from a first memory engine in a plurality of memory engines, wherein the plurality of sub-instruction requests are associated with a direct memory access (DMA) bitmap manipulation request from a first pipeline, wherein each sub-instruction request corresponds to a data element in the DMA bitmap manipulation request, and wherein the first memory engine is to correspond to the first pipeline. The technology also detects, by the operation engine, one or more arguments in the plurality of sub-instruction requests, sends, by the operation engine, one or more load requests to a DRAM in the plurality of DRAMs in accordance with the one or more arguments, and sends, by the operation engine, one or more store requests to the DRAM in accordance with the one or more arguments, wherein the operation engine is to correspond to the DRAM.
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