公开(公告)号：US20240357839A1

公开(公告)日：2024-10-24

申请号：US18759039

申请日：2024-06-28

申请人： Nitin Ashok Deshpande ,  Omkar Gopalkrishna Karhade ,  Debendra Mallik

发明人： Nitin Ashok Deshpande ,  Omkar Gopalkrishna Karhade ,  Debendra Mallik

IPC分类号： H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908

摘要： Memory stacks including replacement blocks and related methods are disclosed. An example integrated circuit disclosed herein includes a first layer including a memory die, and a second layer including a replacement block communicatively coupled to the memory die, the second layer including and a dielectric shell surrounding the replacement block.

公开(公告)号：US20240355794A1

公开(公告)日：2024-10-24

申请号：US18497039

申请日：2023-10-30

申请人： Samsung Electronics Co., Ltd.

发明人： Choongbin Yim ,  Jongkook Kim ,  Chengtar Wu

IPC分类号： H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H10B80/00

CPC分类号： H01L25/105 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3738 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/83 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83862 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/3511

摘要： A semiconductor package may include: a redistribution layer structure; a semiconductor structure on the redistribution layer structure; a printed circuit board on the redistribution layer structure and extending around a side surface of the semiconductor structure; a molding material extending around the semiconductor structure on the redistribution layer structure; and a silicon interposer on the printed circuit board and the molding material.

公开(公告)号：US20240349520A1

公开(公告)日：2024-10-17

申请号：US18370949

申请日：2023-09-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Moorym CHOI ,  Sunil SHIM ,  Seungwoo PAEK ,  Jimin LEE

IPC分类号： H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC分类号： H10B80/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L24/48 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/059

摘要： A semiconductor device includes bonded circuit and cell regions. The cell region includes a substrate, a base memory portion, and a bonding memory portion. Here, base memory portion includes a first gate stacking structure on the substrate and having first and second surfaces, a first channel structure penetrating the first gate stacking structure, and a base bonding pad on the second surface and connected to the first channel structure. The bonding memory portion includes a second gate stacking structure having a third surface bonded to the base memory portion and a fourth surface bonded to the circuit region, a second channel structure penetrating the second gate stacking structure, a first bonding pad connected to the second channel structure in the third surface and bonded to the base bonding pad, and a second bonding pad connected to the second channel structure in the fourth surface and bonded to the circuit region.

公开(公告)号：US20240349507A1

公开(公告)日：2024-10-17

申请号：US18362688

申请日：2023-07-31

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H10B43/35 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B80/00

CPC分类号： H10B43/35 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A semiconductor device includes a gate structure located between a bit line and a source structure, the gate structure including stacked word lines. The semiconductor device also includes a select line structure located between the gate structure and the source structure, the select line structure including an epitaxial pattern and a silicide layer. The semiconductor device further includes a channel structure extending through the gate structure and the select line structure, the channel structure connected between the source structure and the bit line.

公开(公告)号：US20240341094A1

公开(公告)日：2024-10-10

申请号：US18522352

申请日：2023-11-29

申请人： Samsung Electronics Co., Ltd.

发明人： Jiyoun Seo ,  Daeho Kim ,  Su Jong Kim ,  Sangho Rha ,  Byung-Sun Park ,  Mingyu Jeon

IPC分类号： H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC分类号： H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/0651

摘要： A semiconductor device may include a substrate including a cell array region and a connection region, a stack including electrodes, which are vertically stacked on the substrate, and which have a staircase structure in the connection region, channel regions provided on the cell array region that vertically extend through the stack, and a planarization insulating layer that covers the stack in the connection region. The planarization insulating layer may include a first insulating layer in contact with the stack and a second insulating layer that covers the first insulating layer. The first insulating layer may include high-density plasma (HDP) oxide, which is doped with first dopants, and the second insulating layer may include tetraethyl orthosilicate (TEOS) oxide, which is doped with second dopants.

公开(公告)号：US20240332212A1

公开(公告)日：2024-10-03

申请号：US18191085

申请日：2023-03-28

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wen-Yi Lin ,  Yi-Che Chiang ,  Chien-Chen Li ,  Chien-Li Kuo ,  Kuo-Chio Liu

IPC分类号： H01L23/00 ,  H01L25/00 ,  H10B80/00

CPC分类号： H01L23/562 ,  H01L25/50 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： A package structure includes a package substrate, a semiconductor die module on the package substrate, a ring structure on the package substrate adjacent to the semiconductor die module, and a hybrid adhesive having a first modulus and a second modulus less than the first modulus and attaching the ring structure to the package substrate.

公开(公告)号：US20240332110A1

公开(公告)日：2024-10-03

申请号：US18361147

申请日：2023-07-28

申请人： Western Digital Technologies, Inc.

发明人： Rotem Sela ,  Mahmud Asfur ,  Boaz Greenberg

IPC分类号： H01L23/32 ,  H01L23/00 ,  H01L23/40 ,  H01L23/498 ,  H01L25/18 ,  H01R13/502 ,  H01R33/88 ,  H10B80/00

CPC分类号： H01L23/32 ,  H01L23/40 ,  H01L23/49833 ,  H01L24/72 ,  H01L25/18 ,  H01R13/502 ,  H01R33/88 ,  H10B80/00 ,  H01L23/49811 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/72

摘要： A multi-chip package includes a substrate, a first semiconductor module mounted on the substrate, an interposer mounted on the first semiconductor module and a second semiconductor module detachably coupled to the interposer. A housing at least partially encloses the first and second semiconductor modules and the interposer. The housing is configured to transition between a closed configuration and an open configuration. In the closed configuration, the second semiconductor module is fixed in position relative to the interposer and electrically connected to the substrate via the interposer, and in the open configuration the second semiconductor module is detachable from the interposer. The second semiconductor module being detachable from the interposer allows for the second semiconductor module to be selectively replaced to improve the longevity of the multi-chip package.

公开(公告)号：US20240331782A1

公开(公告)日：2024-10-03

申请号：US18539914

申请日：2023-12-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Junyeong Seok ,  Beomkyu Shin ,  Eunchu Oh

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC分类号： G11C16/3431 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A memory block is divided into sub blocks including a first sub block and a second sub block that are disposed in a vertical direction where the memory block includes a plurality of cell strings and each cell string includes a plurality of memory cells that are disposed in the vertical direction. A normal erase operation is performed independently with respect to each of the sub blocks. A disturbance verification read operation with respect to the first sub block is performed to determine whether a threshold voltage of memory cells connected to a wordline in an erased state of the first sub block is increased higher than a reference level. A post erase operation is selectively performed based on a result of the disturbance verification read operation to decrease the threshold voltage of memory cells in the erased state of the first sub block.

公开(公告)号：US20240324249A1

公开(公告)日：2024-09-26

申请号：US18595303

申请日：2024-03-04

申请人： Kioxia Corporation

发明人： Kouji MATSUO

IPC分类号： H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A plurality of memory cell regions includes a semiconductor layer extending in a first direction and a pillar having a side surface in contact with the semiconductor layer and extending in a second direction. A first conductor includes a first portion extending in the first direction and a plurality of second portions extending in a third direction and connected to the first portion. One of the second portions is in contact with the semiconductor layer. Each of a plurality of contact regions includes a plurality of contacts extending in the second direction. A plurality of groups is arranged in the first direction when viewed in the second direction, each of the groups including one of the plurality of memory cell regions, one of the plurality of second portions, and one of the plurality of contact regions, which are arranged in the first direction when viewed in the second direction.

公开(公告)号：US20240321839A1

公开(公告)日：2024-09-26

申请号：US18530542

申请日：2023-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： Kyungdon Mun ,  Kyounglim Suk ,  Jihwang Kim

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H10B80/00

CPC分类号： H01L25/105 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434

摘要： A semiconductor package includes a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern, a first lower semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first lower semiconductor device on the first redistribution structure, a plurality of vertical connection conductors in the molding layer and electrically connected to the first redistribution pattern, a heat dissipation plate disposed on an upper surface of the first lower semiconductor device, and a plurality of upper semiconductor devices disposed on the molding layer and on the first lower semiconductor device, each of the plurality of upper semiconductor devices vertically overlapping a different respective region of the first lower semiconductor device.