公开(公告)号：US20240363464A1

公开(公告)日：2024-10-31

申请号：US18767895

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

摘要： A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

公开(公告)号：US12119338B2

公开(公告)日：2024-10-15

申请号：US18447655

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC分类号： H01L21/44 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/85399

摘要： Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US12119323B2

公开(公告)日：2024-10-15

申请号：US17944018

申请日：2022-09-13

申请人： KIOXIA CORPORATION

发明人： Soichi Homma

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06582

摘要： According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light.

公开(公告)号：US20240341094A1

公开(公告)日：2024-10-10

申请号：US18522352

申请日：2023-11-29

申请人： Samsung Electronics Co., Ltd.

发明人： Jiyoun Seo ,  Daeho Kim ,  Su Jong Kim ,  Sangho Rha ,  Byung-Sun Park ,  Mingyu Jeon

IPC分类号： H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC分类号： H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/0651

摘要： A semiconductor device may include a substrate including a cell array region and a connection region, a stack including electrodes, which are vertically stacked on the substrate, and which have a staircase structure in the connection region, channel regions provided on the cell array region that vertically extend through the stack, and a planarization insulating layer that covers the stack in the connection region. The planarization insulating layer may include a first insulating layer in contact with the stack and a second insulating layer that covers the first insulating layer. The first insulating layer may include high-density plasma (HDP) oxide, which is doped with first dopants, and the second insulating layer may include tetraethyl orthosilicate (TEOS) oxide, which is doped with second dopants.

公开(公告)号：US20240332171A1

公开(公告)日：2024-10-03

申请号：US18614921

申请日：2024-03-25

申请人： ROHM CO., LTD.

发明人： Keiji WADA

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC分类号： H01L23/5227 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/08 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/08245 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2924/0665 ,  H01L2924/182

摘要： An insulation chip includes a first unit, and a second unit bonded to the first unit and smaller in size than the first unit in a plan view. The first unit includes a first element insulating layer, a first insulating element buried in the first element insulating layer, and a first electrode pad provided on the first element insulating layer. The second unit includes a second element insulating layer, and a second insulating element buried in the second element insulating layer. In a unit bonding state in which the second unit is bonded to the first unit, the first and second insulating elements are arranged to face each other in a thickness direction of the first element insulating layer, and the first electrode pad is provided at a different position from the second unit in a plan view.

公开(公告)号：US12087618B2

公开(公告)日：2024-09-10

申请号：US17231163

申请日：2021-04-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng Tang ,  Fu-Chen Chang ,  Cheng-Lin Huang ,  Wen-Ming Chen ,  Chun-Yen Lo ,  Kuo-Chio Liu

IPC分类号： H01L21/768 ,  H01L21/304 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L21/76802 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/67011 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/48 ,  H01L23/481 ,  H01L24/11 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.

公开(公告)号：US12080677B2

公开(公告)日：2024-09-03

申请号：US17693886

申请日：2022-03-14

申请人： Kioxia Corporation

发明人： Katsuya Murakami

IPC分类号： H01L23/00 ,  H01L25/065 ,  H05K1/11

CPC分类号： H01L24/73 ,  H01L24/13 ,  H01L24/48 ,  H01L25/0657 ,  H05K1/111 ,  H01L2224/13021 ,  H01L2224/13028 ,  H01L2224/48491 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

摘要： A board unit according to an embodiment includes a circuit board, a semiconductor device, and a wire. The semiconductor device has a bottom surface facing the circuit board. The semiconductor device includes a plurality of bonding members between the circuit board and the bottom surface. The wire is disposed between the circuit board and the bottom surface. The bonding members have a first row and a second row. Two or more bonding members align in the first row in a first direction. Two or more bonding members align in the second row in the first direction. The second row is apart from the first row in a second direction intersecting with the first direction. The wire includes a first portion disposed between the first row and the second row, and the wire has a strength higher than that of one of the bonding members.

公开(公告)号：US12074139B2

公开(公告)日：2024-08-27

申请号：US17439402

申请日：2020-04-24

申请人： Resonac Corporation

发明人： Tatsuya Yahata ,  Kohei Taniguchi ,  Shintaro Hashimoto ,  Yoshinobu Ozaki ,  Kei Itagaki

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06582

摘要： A support piece formation laminate film according to the present disclosure includes a base material film, a pressure-sensitive adhesive layer, and a support piece formation film, in this order, in which the support piece formation film has a multi-layer structure including at least a metal layer. The support piece formation laminate film is applied to a manufacturing process of a semiconductor device having a dolmen structure including a substrate, a first chip disposed on the substrate, a plurality of support pieces disposed around the first chip, on the substrate, and a second chip disposed to be supported by the plurality of support pieces and to cover the first chip.

公开(公告)号：US20240274578A1

公开(公告)日：2024-08-15

申请号：US18407428

申请日：2024-01-08

申请人： Micron Technology, Inc.

发明人： Jong Sik Paek

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H10B80/00

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

摘要： A semiconductor device assembly is provided. The semiconductor device assembly includes a first semiconductor die electrically coupled with a redistribution layer through first conductive structures. A stack of semiconductor dies is mounted on the first semiconductor die and electrically coupled with the redistribution layer. For example, a base die of the stack of semiconductor dies is mounted on the first semiconductor die, and second conductive structures electrically couple the base die with the redistribution layer. The semiconductor dies in the stack of semiconductor dies are electrically coupled through one or more wires. In doing so, a compact and reliable semiconductor device may be assembled.

公开(公告)号：US12057434B2

公开(公告)日：2024-08-06

申请号：US17977164

申请日：2022-10-31

申请人： Amkor technology Singapore Holding Pte. Ltd.

发明人： Jin Seong Kim ,  Edwin J. Adlam ,  Ludovico E. Bancod ,  Gi Jung Kim ,  Robert Lanzone ,  Jae Ung Lee ,  Yung Woo Lee ,  Mi Kyeong Choi

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/552 ,  H01L25/50 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

摘要： A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.