公开(公告)号：US20250048628A1

公开(公告)日：2025-02-06

申请号：US18437604

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOONYOUNG KWON ,  JIYOUNG KIM ,  JUNHYOUNG KIM ,  SUKKANG SUNG

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: The present disclosure relates to three-dimensional (3D) semiconductor memory devices and electronic systems. An example 3D semiconductor memory device comprises a peripheral circuit structure on a peripheral substrate, a stack structure that includes a plurality of gate electrodes stacked on the peripheral circuit structure, an n-doped pattern on the stack structure, a vertical structure that extends through the stack structure into the n-doped pattern, a p-doped pattern on the n-doped pattern, and an undoped pattern between the n-doped pattern and then p-doped pattern. The p-doped pattern includes a p-doped horizontal pattern on the undoped pattern, and a p-doped vertical pattern that extends through the undoped pattern and the n-doped pattern and that contacts with the vertical structure.

公开(公告)号：US12219774B2

公开(公告)日：2025-02-04

申请号：US17443448

申请日：2021-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Jae Lee ,  Jin Do Byun ,  Young-Hoon Son ,  Young Don Choi ,  Pan Suk Kwak ,  Myung Hun Lee ,  Jung Hwan Choi

IPC: H10B43/40 ,  G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27

Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.

公开(公告)号：US12219772B2

公开(公告)日：2025-02-04

申请号：US16983664

申请日：2020-08-03

Applicant: Lodestar Licensing Group, LLC

Inventor： Akira Goda ,  Haitao Liu ,  Jin Chen ,  Guangyu Huang ,  Mojtaba Asadirad

IPC: H10B43/40 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/04 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L29/08

Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

公开(公告)号：US12200938B2

公开(公告)日：2025-01-14

申请号：US18497790

申请日：2023-10-30

Applicant: Lodestar Licensing Group LLC

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/115 ,  G11C16/08 ,  H01L21/28 ,  H01L23/532 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US12185534B2

公开(公告)日：2024-12-31

申请号：US17649562

申请日：2022-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Byunggon Park ,  Seungmin Lee ,  Kangmin Kim ,  Taemin Eom ,  Byungkwan You

IPC: H10B41/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/60 ,  H01L27/02 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: An integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.

公开(公告)号：US12159843B2

公开(公告)日：2024-12-03

申请号：US17472474

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Daisuke Kawamura

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device according to an embodiment includes a lower layer wiring and a dummy wiring arranged in a first hierarchy, a contact arranged in a second hierarchy above the first hierarchy and connected to the lower layer wiring, and first and second plate-like portions arranged in the second hierarchy, extending in a stacking direction of each layer belonging to the second hierarchy and in a first direction intersecting with the stacking direction, and sandwiching the contact in a second direction intersecting with the stacking direction and the first direction at a position away from the contact, and the dummy wiring has at least three edges arranged at respective positions overlapping with one of the first and second plate-like portions in the stacking direction, and an orientation in which at least one of the three edges intersects with the first or second plate-like portion differs as viewed from the stacking direction from orientations in which the other edges intersect with the first or second plate-like portion.

公开(公告)号：US20240395592A1

公开(公告)日：2024-11-28

申请号：US17942109

申请日：2022-09-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

Abstract: A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.

公开(公告)号：US20240379502A1

公开(公告)日：2024-11-14

申请号：US18778977

申请日：2024-07-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L21/74 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/118 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/808 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B63/00

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.

公开(公告)号：US20240341097A1

公开(公告)日：2024-10-10

申请号：US18746954

申请日：2024-06-18

Applicant: SK hynix Inc.

Inventor： Nam Jae LEE

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stacked body, an insulating layer overlapping the gate stacked body, a first source layer including a horizontal portion between the gate stacked body and the insulating layer and a protrusion extending from the horizontal portion so as to penetrate the insulating layer, a channel layer penetrating the gate stacked body and extending into the horizontal portion of the first source layer, a first memory pattern between the channel layer and the gate stacked body, and a second source layer disposed between the gate stacked body and the first source layer and coming in contact with the channel layer.

公开(公告)号：US20240332385A1

公开(公告)日：2024-10-03

申请号：US18739179

申请日：2024-06-10

Applicant: LONGITUDE FLASH MEMORY SOLUTIONS LTD.

Inventor： Igor Polishchuk ,  Sagy Charel Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/423 ,  B82Y10/00 ,  G11C16/04 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L29/4234 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02532 ,  H01L21/02595 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.