公开(公告)号：US20250063729A1

公开(公告)日：2025-02-20

申请号：US18666514

申请日：2024-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Joonyoung Kwon ,  Siwan Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B41/35 ,  H01L23/00 ,  H01L25/18 ,  H10B12/00 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a plate layer; conductive layers spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer, extending by different lengths in a second direction perpendicular to the first direction, and forming a staircase region; a gap-fill insulating layer on the staircase region; and vertical structures penetrating through the gap-fill insulating layer and the conductive layers in the staircase region and extending in the first direction, and wherein the gap-fill insulating layer includes voids disposed symmetrically with respect to at least one of the vertical structures or a center of the staircase region in a third direction perpendicular to the first direction and the second direction.

公开(公告)号：US12167601B2

公开(公告)日：2024-12-10

申请号：US18188946

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Manjoong Kim

IPC: H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US11437396B2

公开(公告)日：2022-09-06

申请号：US17032128

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US11069698B2

公开(公告)日：2021-07-20

申请号：US16398442

申请日：2019-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kwang-Soo Kim ,  Geunwon Lim ,  Jisung Cheon

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/311

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

公开(公告)号：US12207469B2

公开(公告)日：2025-01-21

申请号：US18386112

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Seonho Yoon ,  Bonghyun Choi

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US12185534B2

公开(公告)日：2024-12-31

申请号：US17649562

申请日：2022-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Byunggon Park ,  Seungmin Lee ,  Kangmin Kim ,  Taemin Eom ,  Byungkwan You

IPC: H10B41/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/60 ,  H01L27/02 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: An integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.

公开(公告)号：US20240389365A1

公开(公告)日：2024-11-21

申请号：US18786162

申请日：2024-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Lee ,  Junhyoung Kim ,  Youngbum Woo ,  Joonsung Lim

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices disposed on the first substrate, and first metal bonding layers disposed on the circuit devices, and a second semiconductor structure including gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to upper surfaces of the first metal bonding layers, channel structures passing through the gate electrodes, extending in the first direction, and respectively including a channel layer, second metal bonding layers disposed below the channel structures and the gate electrodes and connected to the first metal bonding layers, bit lines disposed below the channel structures, extending in a second direction, perpendicular to the first direction, and spaced apart from each other, and source lines disposed on the channel structures, extending in a third direction, perpendicular to the second direction, and spaced apart from each other. The channel structures are respectively disposed in intersection regions in which the bit lines and the source lines intersect each other.

公开(公告)号：US11637121B2

公开(公告)日：2023-04-25

申请号：US16802736

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Manjoong Kim

IPC: H01L27/11519 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US11626413B2

公开(公告)日：2023-04-11

申请号：US17749486

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157

Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

公开(公告)号：US20230005949A1

公开(公告)日：2023-01-05

申请号：US17720453

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Lee ,  Kangmin Kim ,  Junhyoung Kim ,  Yonghoon Son ,  Joonsung Lim

IPC: H01L27/11575 ,  H01L23/535 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other. The second insulating layers include the same material as the interlayer insulating layers.